Inventor profile of:

Hao Chen

City:

San Ramon, California

Country:

United States

Published Applications:

29

Last publication date:

2020-10-29

Top Assignees for applications by Hao Chen

The entities that hold a legal rights for patent applications filed by inventor Chen Hao:

Recent patent applications by Chen Hao

Hao Chen from San Ramon, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-10-29
US20200341533A1
Physics

Power throttling in a multicore system

#2 | 2017-11-09
US20170322614A1
Physics

Power management techniques

#3 | 2015-10-22
US20150302544A1
Physics

Coordinate based QoS escalation

#4 | 2015-04-02
US20150095630A1
Physics

Global configuration broadcast

#5 | 2015-03-12
US20150070365A1
Physics

Arbitration method for multi-request display pipeline

#6 | 2015-03-05
US20150062134A1
Physics

PARAMETER FIFO FOR CONFIGURING VIDEO RELATED SETTINGS

#7 | 2014-10-07
US13313327
-

Matrix for numerical comparison

#8 | 2014-08-21
US20140237195A1
Physics

N-DIMENSIONAL COLLAPSIBLE FIFO

#9 | 2014-08-21
US20140232731A1
Physics

Power management for image scaling circuitry

#10 | 2014-03-27
US20140085320A1
Physics

EFFICIENT PROCESSING OF ACCESS REQUESTS FOR A SHARED RESOURCE

#11 | 2014-02-20
US20140052937A1
Physics

Dynamic QoS upgrading

#12 | 2014-01-02
US20140006743A1
Physics

QoS-aware scheduling

#13 | 2013-03-14
US20130064025A1
Physics

Dynamic data strobe detection

#14 | 2013-02-28
US20130054902A1
Physics

Accelerating memory operations blocked by ordering requirements and data not yet received

#15 | 2013-02-28
US20130054901A1
Physics

Proportional memory operation throttling

#16 | 2013-02-21
US20130046938A1
Physics

QoS-aware scheduling

#17 | 2012-06-21
US20120159230A1
Physics

Mechanism for Updating Memory Controller Timing Parameters During a Frequency Change

#18 | 2012-05-31
US20120137078A1
Physics

Multiple critical word bypassing in a memory controller

#19 | 2012-05-24
US20120126868A1
Electricity

Mechanism for an efficient DLL training protocol during a frequency change

#20 | 2012-03-22
US20120072787A1
Physics

Memory controller with loopback test interface

#21 | 2012-03-22
US20120072679A1
Physics

Reordering in the memory controller

#22 | 2012-03-22
US20120072678A1
Physics

Dynamic QoS upgrading

#23 | 2012-03-22
US20120072677A1
Physics

Multi-Ported Memory Controller with Ports Associated with Traffic Classes

#24 | 2012-03-22
US20120069034A1
Physics

Memory controller with QoS-aware scheduling

#25 | 2012-01-19
US20120017135A1
Electricity

Combined single error correction/device kill detection code

#26 | 2011-12-01
US20110296110A1
Physics

Critical word forwarding with adaptive prediction

#27 | 2011-02-10
US20110035560A1
Physics

Memory controller with loopback test interface

#28 | 2008-12-11
US20080307286A1
Electricity

Combined single error correction/device kill detection code

#29 | 2008-12-11
US20080307276A1
Physics

Memory controller with loopback test interface

InventorID:

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