Altdorf
Germany
10
2024-02-01
The entities that hold a legal rights for patent applications filed by inventor Daellenbach Lukas:
Lukas Daellenbach from Altdorf, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
MULTI-LAYER INTEGRATED CIRCUIT ROUTING TOOL
#2 | 2022-01-06Semiconductor circuit design and unit pin placement
#3 | 2021-03-04Sink-based wire tagging in multi-sink integrated circuit net
#4 | 2020-02-13RE-ROUTING TIME CRITICAL MULTI-SINK NETS IN CHIP DESIGN
#5 | 2018-06-14Timing based net constraints tagging with zero wire load validation
#6 | 2018-06-14Optimizing routing of a signal path in a semiconductor device
#7 | 2016-08-11Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS)
#8 | 2016-08-11Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS)
#9 | 2013-02-21Early noise detection and noise aware routing in circuit design
#10 | 2008-12-04Method and system for routing of integrated circuit design
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