Austin, Texas
United States
35
2018-04-12
The entities that hold a legal rights for patent applications filed by inventor FIELDS, JR. James S.:
James S. FIELDS, JR. from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Buffered automated flash controller connected directly to processor memory bus
#2 | 2016-09-08Buffered automated flash controller connected directly to processor memory bus
#3 | 2016-02-11Buffered automated flash controller connected directly to processor memory bus
#4 | 2016-01-07Buffered automated flash controller connected directly to processor memory bus
#5 | 2015-01-22Dynamic formation of symmetric multi-processor (SMP) domains
#6 | 2009-05-21Recovery from a hang condition in a data processing system
#7 | 2008-11-27Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations
#8 | 2008-09-11Ticket-based operation tracking
#9 | 2008-09-04Switching a defective signal line with a spare signal line without shutting down the computer system
#10 | 2008-09-04Data processing system and method for efficient communication utilizing an in coherency state
#11 | 2008-08-28Data processing system, method and interconnect fabric supporting destination data tagging
#12 | 2008-07-31Interconnect fabric for a data processing system
#13 | 2008-06-19Implementing an enhanced hover state with active prefetches
#14 | 2008-05-22Protecting ownership transfer with non-uniform protection windows
#15 | 2008-05-22Protecting ownership transfer with non-uniform protection windows
#16 | 2008-03-20Coherency management of castouts
#17 | 2007-12-27Method for interfacing components of a computing system with a pair of unidirectional, point-to-point buses
#18 | 2007-09-27Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response
#19 | 2007-06-21Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses
#20 | 2007-04-19Data processing system and method in which a participant initiating a read operation protects data integrity
#21 | 2007-03-29Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes
#22 | 2007-03-15System and method for recovering from a hang condition in a data processing system
#23 | 2006-11-30Data processing system, cache system and method for passively scrubbing a domain indication
#24 | 2006-11-30Data processing system, cache system and method for actively scrubbing a domain indication
#25 | 2006-11-30Data processing system, cache system and method for scrubbing a domain indication in response to execution of program code
#26 | 2006-08-24Method and apparatus for invalidating entries within a translation control entry (TCE) cache
#27 | 2006-08-24Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations
#28 | 2006-08-17Switching a defective signal line with a spare signal line without shutting down the computer system
#29 | 2006-08-10Processors interconnect fabric with relay broadcasting and accumulation of partial responses
#30 | 2006-08-10Data processing system, method and interconnect fabric supporting destination data tagging
#31 | 2006-08-10Data processing system and method for efficient communication utilizing an in coherency state
#32 | 2006-08-10Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory
#33 | 2006-08-10Data processing system and method for predictively selecting a scope of broadcast of an operation
#34 | 2006-08-10Method and apparatus for performing data prefetch in a multiprocessor system
#35 | 2006-08-10Data processing system, method and interconnect fabric for selective link information allocation in a data processing system
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