Austin, Texas
United States
32
2017-03-09
The entities that hold a legal rights for patent applications filed by inventor GASKINS STEPHAN:
STEPHAN GASKINS from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Core ID designation system for dynamically designated bootstrap processor
#2 | 2017-01-05Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state
#3 | 2016-12-01Multi-core data array power gating restoral mechanism
#4 | 2016-12-01Propagation of updates to per-core-instantiated architecturally-visible storage resource
#5 | 2016-10-06Cache memory diagnostic writeback
#6 | 2016-06-23Multi-core programming apparatus and method for restoring data arrays following a power gating event
#7 | 2016-06-23Multi-core microprocessor power gating cache restoral programming mechanism
#8 | 2016-06-23Multi-core data array power gating cache restoral programming mechanism
#9 | 2016-06-23Multi-core programming apparatus and method for restoring data arrays following a power gating event
#10 | 2015-11-26Apparatus and method for repairing cache arrays in a multi-core microprocessor
#11 | 2015-11-26Multi-core microprocessor power gating cache restoral mechanism
#12 | 2015-11-26Multi-core data array power gating restoral mechanism
#13 | 2015-11-26Multi-core apparatus and method for restoring data arrays following a power gating event
#14 | 2015-07-30Dynamic cache enlarging by counting evictions
#15 | 2015-03-05Propagation of microcode patches to multiple cores in multicore microprocessor
#16 | 2015-03-05Selective designation of multiple cores as bootstrap processor in a multi-core microprocessor
#17 | 2015-03-05Propagation of updates to per-core-instantiated architecturally-visible storage resource
#18 | 2015-03-05Inter-core communication via uncore RAM
#19 | 2015-03-05Service processor patch mechanism
#20 | 2015-03-05Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor
#21 | 2015-03-05Single core wakeup multi-core synchronization mechanism
#22 | 2015-02-12Reconfigurably designating master core for conditional output on sideband communication wires distinct from system bus
#23 | 2012-06-28Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
#24 | 2012-05-08Microprocessor that performs adaptive power throttling
#25 | 2012-02-23Multicore processor power credit management to allow all processing cores to operate at elevated frequency
#26 | 2012-02-23Microprocessor with multicore processor power credit management feature
#27 | 2012-01-05Multicore processor power credit management in which multiple processing cores use shared memory to communicate individual energy consumption
#28 | 2011-02-10Detection of fuse re-growth in a microprocessor
#29 | 2011-02-10Detection of uncorrectable re-grown fuses in a microprocessor
#30 | 2010-09-09Microprocessor that performs adaptive power throttling
#31 | 2007-11-01Microprocessor capable of dynamically increasing its performance in response to varying operating temperature
#32 | 2007-10-25Microprocessor capable of dynamically reducing its power consumption in response to varying operating temperature
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