Inventor profile of:

Steven C. Bartling

City:

Plano, Texas

Country:

United States

Published Applications:

23

Last publication date:

2015-03-12

Top Assignees for applications by Steven C. Bartling

The entities that hold a legal rights for patent applications filed by inventor Bartling Steven C.:

Recent patent applications by Bartling Steven C.

Steven C. Bartling from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2015-03-12
US20150070061A1
Electricity

Dual-port negative level sensitive reset preset data retention latch

#2 | 2015-02-26
US20150054557A1
Electricity

Dual-port negative level sensitive preset data retention latch

#3 | 2015-02-26
US20150054545A1
Electricity

Dual-port positive level sensitive reset preset data retention latch

#4 | 2015-02-26
US20150054544A1
Electricity

Dual-port positive level sensitive preset data retention latch

#5 | 2010-12-30
US20100332929A1
Physics

Scan testable register file

#6 | 2009-01-15
US20090015413A1
Physics

WIRELESSLY TRANSMITTING BIOLOGICAL PARAMETERS

#7 | 2008-10-23
US20080259681A1
Physics

Systems and devices for implementing sub-threshold memory devices

#8 | 2008-10-23
US20080258790A1
Electricity

Systems and Devices for Sub-threshold Data Capture

#9 | 2007-10-04
US20070229135A1
Electricity

Apparatus and method for generating pulses

#10 | 2007-05-17
US20070113048A1
Physics

Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content

#11 | 2007-01-25
US20070022344A1
Physics

Digital storage element architecture comprising dual scan clocks and gated scan output

#12 | 2007-01-25
US20070022339A1
Physics

Digital design component with scan clock generation

#13 | 2007-01-25
US20070022336A1
Physics

Digital storage element with enable signal gating

#14 | 2007-01-04
US20070006109A1
Physics

Method and system for correcting signal integrity crosstalk violations

#15 | 2007-01-04
US20070006106A1
Physics

Method and system for desensitization of chip designs from perturbations affecting timing and manufacturability

#16 | 2007-01-04
US20070006105A1
Physics

Method and system for synthesis of flip-flops

#17 | 2007-01-04
US20070001733A1
Physics

Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality

#18 | 2007-01-04
US20070001732A1
Physics

Digital storage element with dual behavior

#19 | 2007-01-04
US20070001731A1
Electricity

Digital storage element architecture comprising integrated multiplexer and reset functionality

#20 | 2007-01-04
US20070001730A1
Electricity

Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality

#21 | 2007-01-04
US20070001729A1
Electricity

Digital storage element architecture comprising dual scan clocks and preset functionality

#22 | 2007-01-04
US20070001728A1
Electricity

Digital storage element architecture comprising dual scan clocks and reset functionality

#23 | 2006-10-12
US20060226885A1
Electricity

Apparatus and method for generating pulses

InventorID:

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