Dresden
Germany
23
2025-09-04
The entities that hold a legal rights for patent applications filed by inventor Herrmann Tom:
Tom Herrmann from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
CAPACITIVE JUNCTION BETWEEN CONDUCTIVE LINE AND CONDUCTIVE PILLAR WITH METHODS TO FORM SAME
#2 | 2025-04-24NONVOLATILE MEMORY WITH ISOLATION STRUCTURE AND METHOD OF FORMING THE SAME
#3 | 2024-05-23STRUCTURE WITH BACK-GATE HAVING OPPOSITELY DOPED SEMICONDUCTOR REGIONS
#4 | 2024-02-15STRUCTURE INCLUDING TRANSISTOR USING BURIED INSULATOR LAYER AS GATE DIELECTRIC AND TRENCH ISOLATIONS IN SOURCE AND DRAIN
#5 | 2023-06-22Structure including transistor using buried insulator layer as gate dielectric and trench isolations in source and drain
#6 | 2022-03-17Charge-trapping sidewall spacer-type non-volatile memory device and method
#7 | 2021-12-16Floating-gate devices in high voltage applications
#8 | 2020-05-05Buried-channel low noise transistors and methods of making such devices
#9 | 2019-05-23Laterally double diffused metal oxide semiconductor (LDMOS) device on fully depleted silicon on insulator (FDSOI) enabling high input voltage
#10 | 2019-05-07Thin body field effect transistor including a counter-doped channel area and a method of forming the same
#11 | 2019-04-11Transistor element with reduced lateral electrical field
#12 | 2019-02-14Fully depleted silicon on insulator (FDSOI) lateral double-diffused metal oxide semiconductor (LDMOS) for high frequency applications
#13 | 2018-11-06Resistor structure with high resistance based on very thin semiconductor layer
#14 | 2018-03-29Capacitive structure in a semiconductor device having reduced capacitance variability
#15 | 2017-02-28Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure
#16 | 2017-02-16Semiconductor structure including a nonvolatile memory cell and method for the formation thereof
#17 | 2014-07-24Method of forming a semiconductor structure including a vertical nanowire
#18 | 2014-01-30Threshold voltage adjustment in a fin transistor by corner implantation
#19 | 2013-10-24Integrated circuits having protruding source and drain regions and methods for forming integrated circuits
#20 | 2013-09-05MULTIPLE STEP IMPLANT PROCESS FOR FORMING SOURCE/DRAIN REGIONS ON SEMICONDUCTOR DEVICES
#21 | 2013-07-18Strain engineering in three-dimensional transistors based on strained isolation material
#22 | 2013-02-28Threshold voltage adjustment in a Fin transistor by corner implantation
#23 | 2012-10-18Stabilized metal silicides in silicon-germanium regions of transistor elements
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