Inventor profile of:

Pierre Morin

City:

Grenoble

Country:

France

Published Applications:

15

Last publication date:

2018-11-08

Top Assignees for applications by Pierre Morin

The entities that hold a legal rights for patent applications filed by inventor Morin Pierre:

Recent patent applications by Morin Pierre

Pierre Morin from Grenoble, FR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-11-08
US20180323237A1
Electricity

Phase-change memory

#2 | 2018-10-18
US20180301625A1
Electricity

Phase change memory

#3 | 2018-01-25
US20180026136A1
Electricity

Semiconductor device with fin and related methods

#4 | 2018-01-04
US20180006154A1
Electricity

Semiconductor device including optimized elastic strain buffer

#5 | 2017-11-30
US20170345935A1
Electricity

Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate

#6 | 2017-09-14
US20170263607A1
Electricity

Method for fabricating a device with a tensile-strained NMOS transistor and a uniaxial compression strained PMOS transistor

#7 | 2017-09-14
US20170263495A1
Electricity

Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions

#8 | 2017-08-03
US20170221903A1
Electricity

Method to form localized relaxed substrate by using condensation

#9 | 2017-07-13
US20170200653A1
Electricity

Co-integration of tensile silicon and compressive silicon germanium

#10 | 2017-06-01
US20170154900A1
Electricity

INTEGRATED TENSILE STRAINED SILICON NFET AND COMPRESSIVE STRAINED SILICON-GERMANIUM PFET IMPLEMENTED IN FINFET TECHNOLOGY

#11 | 2017-01-12
US20170012127A1
Electricity

Semiconductor device with fin and related methods

#12 | 2013-02-28
US20130049163A1
Electricity

Insulation wall between transistors on SOI

#13 | 2007-09-20
US20070215919A1
Electricity

Reduction of threshold voltage instabilities in a MOS transistor

#14 | 2007-03-29
US20070069256A1
Electricity

Semiconductor device comprising at least one MOS transistor having an etch stop layer, and corresponding fabrication process

#15 | 2007-03-06
US10701165
-

Semiconductor device with MOS transistors with an etch-stop layer having an improved residual stress level and method for fabricating such a semiconductor device

InventorID:

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