Michael Bertone

Managing potential faults for speculative page table access

Managing commit order for an external instruction relative to queued instructions

Managing load and store instructions for memory barrier handling

Managing translation lookaside buffer entries based on associativity and page size

Managing commit order for an external instruction relative to two unissued queued instructions

Managing low-level instructions and core interactions in multi-core processors

Managing fairness for lock and unlock operations using operation prioritization

Managing lock and unlock operations using active spinning

Managing lock and unlock operations using traffic prioritization

Managing lock and unlock operations using operation prediction

Managing virtual-address caches for multiple memory page sizes

Admission control for memory access requests

Collapsed address translation with multiple page sizes

Collapsed address translation with multiple page sizes

Translation bypass in multi-stage address translation

Maintenance of cache and tags in a translation lookaside buffer

Merged TLB structure for multiple sequential address translations