Giorgio Servalli

DOUBLE PATTERNING METHOD TO FORM SUB-LITHOGRAPHIC PILLARS

DOUBLE PATTERNING METHOD TO FORM SUB-LITHOGRAPHIC PILLARS

Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling and device thus obtained

Double patterning method for creating a regular array of pillars with dual shallow trench isolation

Fabricating bipolar junction select transistors for semiconductor memories

PHASE CHANGE MEMORY CELL WITH SELF-ALIGNED VERTICAL HEATER

Fabricating bipolar junction select transistors for semiconductor memories

Process for forming differential spaces in electronics device integrated on a semiconductor substrate

Reference cell layout with enhanced RTN immunity

Process for manufacturing an electronic device integrated on semiconductor substrate comprising non volatile floating gate memories and an associated circuitry and corresponding electronic device

PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE

NON-VOLATILE MEMORY ELECTRONIC DEVICE

Integrated resistive elements with silicidation protection

Process for manufacturing a memory with local electrical contact between the source line and the well

Method for manufacturing electronic non-volatile memory devices integrated in a semiconductor substrate

Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling and device thus obtained

Process for manufacturing integrated resistive elements with silicidation protection

Test structure for the measurement of contact to gate distance in non-volatile memory devices and corresponding test method