Dresden
Germany
26
2013-07-11
The entities that hold a legal rights for patent applications filed by inventor Wirbeleit Frank:
Frank Wirbeleit from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
TRANSISTOR WITH STRESS ENHANCED CHANNEL AND METHODS FOR FABRICATION
#2 | 2013-02-28Fabrication of a semiconductor device with extended epitaxial semiconductor regions
#3 | 2012-08-02Static RAM cell design and multi-contact regime for connecting double channel transistors
#4 | 2011-12-01Transistor with embedded strain-inducing material formed in diamond-shaped cavities based on a pre-amorphization
#5 | 2011-09-15Method for forming a strained transistor by stress memorization based on a stressed implantation mask
#6 | 2011-04-07Body controlled double channel transistor and circuits comprising the same
#7 | 2010-08-12METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
#8 | 2010-03-04Static RAM cell design and multi-contact regime for connecting double channel transistors
#9 | 2009-12-31Three-dimensional transistor with double channel configuration
#10 | 2009-09-24Semiconductor device comprising isolation trenches inducing different types of strain
#11 | 2009-09-03Reduction of memory instability by local adaptation of re-crystallization conditions in a cache area of a semiconductor device
#12 | 2009-08-06Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography steps
#13 | 2009-08-06Body controlled double channel transistor and circuits comprising the same
#14 | 2009-01-01Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure
#15 | 2008-12-04METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING AN IMPLANTATION OF IONS IN A MATERIAL LAYER TO BE ETCHED
#16 | 2008-10-23Stressed MOS device
#17 | 2008-10-02Method of forming a semiconductor structure
#18 | 2008-08-12Stressed MOS device and method for its fabrication
#19 | 2008-07-03Inline stress evaluation in microstructure devices
#20 | 2008-04-03Method of making a semiconductor device comprising isolation trenches inducing different types of strain
#21 | 2008-02-12Semiconductor device having nanowire contact structures and method for its fabrication
#22 | 2008-01-31Method for forming a strained transistor by stress memorization based on a stressed implantation mask
#23 | 2008-01-31Formation of transistor having a strained channel region including a performance enhancing material composition utilizing a mask pattern
#24 | 2007-08-02SRAM cells including self-stabilizing transistor structures
#25 | 2007-03-29Methods for fabrication of a stressed MOS device
#26 | 2006-11-30TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES BY ADAPTING A VERTICAL DOPANT PROFILE
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