Andy Wangkun CHEN

Bitline Precharge Circuitry and Methods

Power Gating Circuitry and Methods

Systems, Methods, and Devices of Design-For-Test Circuitry

Level-Shifting Circuitry Devices and Methods

READ SIGNAL OUTPUT TERMINAL DRIVER

MULTIPLE OR SINGLE VOLTAGE DOMAIN LOGIC GATE CIRCUITRY

CLOCKING SCHEME FOR MULTI-PORT REGISTER FILE

MEMORY POWER DIGITAL MULTIPLEXER

CIRCUIT FOR MULTIPORT REGISTER FILE

RAPID POWER READY SIGNALING IN A MEMORY ARRAY

ACCESS TIME IN A MEMORY ARRAY

INRUSH CURRENT MANAGEMENT IN A MEMORY ARRAY

Systems, Methods, and Devices for a Wordline or a Bitline Formed and Disposed Within a Backside Metal Layer

Dual Wordline Applications in Memory

POWER SAVING MODE CONTROL FOR A MEMORY INSTANCE

Row Repair Circuitry

Power-Gate Structure

Multi-Transistor Bitcell Structure

Skew Cell Architecture

Multi-Port Bitcell Architecture

Multi-port circuit architecture

Buried Metal Techniques for Memory Applications

Memory Testing Techniques

Multi-port bitcell architecture

Circuitry for memory address collision prevention

Circuits and Methods for I/O Circuitry TSV Coupling

Multi-port memory architecture

Configurable scan chain architecture for multi-port memory

TSV Coupled Integrated Circuits and Methods

Flexible sizing and routing architecture

Column redundancy techniques

Multi-tier memory architecture

Row redundancy techniques

Wordline modulation techniques

Wordline driver architecture

Wordline driver architecture

Metal routing techniques

Buried Power Rail Architecture

Memory architecture with pulsed-bias power

Memory architecture with DC biasing

Circuitry apportioning of an integrated circuit

Bitcell architecture using buried metal

Bitcell architecture with buried ground rail

TSV coupled integrated circuits and methods

Backside power supply techniques

Power-gating techniques with buried metal

3D storage architecture with tier-specific controls

Techniques for powering memory

Backside power rail architecture

Buried metal technique for critical signal nets

Cell architecture

Memory embedded full scan for latent defects

Frontside-to-backside intermixing architecture for coupling a frontside network to a backside network

Buried power rail structure for providing multi-domain power supply for memory device

CAM device with 3D CAM cells

Slew-load characterization

Bitcell with multiple read bitlines

Configurable control of integrated circuits

Memory multiplexing techniques

Modular gated multiplier circuitry and multiplication technique

Latch circuitry for memory applications

Read and write techniques

Polarity swapping circuitry

Computer implemented system and method for generating a layout of a cell defining a circuit component

Data compressor logic circuit

Control architecture for column decoder circuitry

Bitcell shifting technique

Memory structure with bitline strapping

Memory testing techniques

Selective clock adjustment during read and/or write memory operations

Wordline decoder circuitry

Data compressor logic circuit

Apparatus and method to access a memory location

Metal layout techniques

Memory testing techniques

Clock generating circuitry

Level shift latch circuitry

Redundancy circuitry for memory application

Error detection and correction circuitry

Multi-port memory circuitry

Latch circuitry for memory applications

Transition coupling circuitry for memory applications

Level shifter with bypass control

Computer implemented system and method for generating a layout of a cell defining a circuit component

Circuit with impedance elements connected to sources and drains of pMOSFET headers

Level shifter with bypass

Power-on-reset circuit

Computer implemented system and method for generating a layout of a cell defining a circuit component

Power-on-reset circuit

Location-based optimization for memory systems

Low power input gating

Error detection circuitry for use with memory

Memory with multiple write ports

Test techniques in memory devices

Double pumped memory techniques

Access suppression in a memory device

Memory circuitry using write assist voltage boost

Level conversion circuit and method

Computer implemented system and method for generating a layout of a cell defining a circuit component

Memory circuitry using write assist voltage boost