Inventor profile of:

Sascha Junghans

City:

Ammerbuch

Country:

Germany

Published Applications:

22

Last publication date:

2024-04-11

Top Assignees for applications by Sascha Junghans

The entities that hold a legal rights for patent applications filed by inventor Junghans Sascha:

Recent patent applications by Junghans Sascha

Sascha Junghans from Ammerbuch, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-04-11
US20240119013A1
Physics

Combining peripheral component interface express partial store commands along cache line boundaries

#2 | 2024-04-11
US20240119000A1
Physics

INPUT/OUTPUT (I/O) STORE PROTOCOL FOR PIPELINING COHERENT OPERATIONS

#3 | 2022-01-06
US20220004412A1
Physics

Directed interrupt virtualization with running indicator

#4 | 2020-08-20
US20200264995A1
Physics

Directed interrupt virtualization with blocking indicator

#5 | 2020-08-20
US20200264910A1
Physics

Directed interrupt virtualization with running indicator

#6 | 2019-10-31
US20190332559A1
Physics

Data transfer using a descriptor

#7 | 2018-12-27
US20180374522A1
Physics

Preinstall of partial store cache lines

#8 | 2018-12-20
US20180365182A1
Physics

Management of data transaction from I/O devices

#9 | 2018-12-20
US20180365180A1
Physics

Management of data transaction from I/O devices

#10 | 2017-11-09
US20170322896A1
Physics

Data transfer using a descriptor

#11 | 2016-05-05
US20160124854A1
Physics

Increased bandwidth of ordered stores in a non-uniform memory subsystem

#12 | 2016-05-05
US20160124653A1
Physics

Increased bandwidth of ordered stores in a non-uniform memory subsystem

#13 | 2016-04-07
US20160098363A1
Physics

Initializing I/O devices

#14 | 2016-02-25
US20160055107A1
Physics

Data processing apparatus and method

#15 | 2016-02-18
US20160048468A1
Physics

Resource allocation by virtual channel management and bus multiplexing

#16 | 2015-12-17
US20150365225A1
Electricity

Tracing data from an asynchronous interface

#17 | 2015-06-04
US20150154139A1
Physics

Resource allocation by virtual channel management and bus multiplexing

#18 | 2015-06-04
US20150154131A1
Physics

Data transfer using a descriptor

#19 | 2015-05-28
US20150149727A1
Physics

Write and read collision avoidance in single port memory devices

#20 | 2015-05-28
US20150149716A1
Physics

Write and read collision avoidance in single port memory devices

#21 | 2015-03-31
US14090060
Physics

Write and read collision avoidance in single port memory devices

#22 | 2014-09-18
US20140281238A1
Physics

Systems and methods for accessing cache memory

InventorID:

1177838 ⎘