Inventor profile of:

Nicolas Maeding

City:

Holzgerlingen

Country:

Germany

Published Applications:

19

Last publication date:

2023-07-27

Top Assignees for applications by Nicolas Maeding

The entities that hold a legal rights for patent applications filed by inventor Maeding Nicolas:

Recent patent applications by Maeding Nicolas

Nicolas Maeding from Holzgerlingen, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-07-27
US20230239148A1
Electricity

Chained manifest for key management and attestation

#2 | 2023-07-13
US20230224156A1
Electricity

Storage encryption for a trusted execution environment

#3 | 2023-04-27
US20230128099A1
Physics

Trusted workload execution

#4 | 2023-04-27
US20230127956A1
Physics

Building and deploying an application

#5 | 2023-02-09
US20230040468A1
Electricity

Deploying a system-specific secret in a highly resilient computer system

#6 | 2018-08-16
US20180231607A1
Physics

Integrated circuit chip and a method for testing the same

#7 | 2017-01-05
US20170003345A1
Physics

Integrated circuit chip and a method for testing the same

#8 | 2015-06-11
US20150160293A1
Physics

Integrated circuit chip and a method for testing the same

#9 | 2011-03-24
US20110072170A1
Physics

Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor

#10 | 2010-08-05
US20100199074A1
Physics

Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance

#11 | 2010-03-04
US20100057825A1
Physics

Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing

#12 | 2009-11-26
US20090292892A1
Physics

Method to reduce power consumption of a register file with multi SMT support

#13 | 2009-10-01
US20090249035A1
Physics

MULTI-CYCLE REGISTER FILE BYPASS

#14 | 2009-01-08
US20090013289A1
Physics

Circuit design optimization of integrated circuit based clock gated memory elements

#15 | 2008-11-20
US20080288901A1
Physics

Formally deriving a minimal clock-gating scheme

#16 | 2008-11-06
US20080276076A1
Physics

Method and apparatus for register renaming

#17 | 2008-08-28
US20080209287A1
Physics

Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes

#18 | 2007-09-27
US20070226664A1
Physics

Method and system for verifying the equivalence of digital circuits

#19 | 2007-01-11
US20070011220A1
Physics

Electronic circuit for implementing a permutation operation

InventorID:

1188824 ⎘