Austin, Texas
United States
140
2024-07-11
The entities that hold a legal rights for patent applications filed by inventor Berke Stuart Allen:
Stuart Allen Berke from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SHARED MEMORY FABRIC WORKLOAD PERFORMANCE SYSTEM
#2 | 2024-07-11RESOURCE-CAPABILITY-AND-CONNECTIVITY-BASED WORKLOAD PERFORMANCE SYSTEM
#3 | 2024-07-11RESOURCE-CAPABILITY-AND-CONNECTIVITY-BASED WORKLOAD PERFORMANCE IMPROVEMENT SYSTEM
#4 | 2024-06-27RUNTIME DE-INTERLEAVE AND RE-INTERLEAVE OF SYSTEM MEMORY
#5 | 2024-06-06Tiered memory management system
#6 | 2024-02-29METHOD TO OFFLOAD MEMORY TIERING FROM THE CPU TO THE MEMORY DEVICE
#7 | 2024-02-01Runtime de-interleave and re-interleave of system memory
#8 | 2024-01-25Providing cache line metadata over multiple cache lines
#9 | 2024-01-25Method for CXL fallback in a CXL system
#10 | 2024-01-25Distributed region tracking for tiered memory systems
#11 | 2024-01-25OPTIMAL MEMORY TIERING OF LARGE MEMORY SYSTEMS USING A MINIMAL NUMBER OF PROCESSORS
#12 | 2024-01-18Method for PCIe fallback in a CXL system
#13 | 2022-05-12MEMORY THERMAL MANAGEMENT DURING INITIALIZATION OF AN INFORMATION HANDLING SYSTEM
#14 | 2021-09-02System and method for variable input output voltage on different channels for increasing power efficiency
#15 | 2021-08-26System and method for determining physical orientation of a memory module using on-board thermal sensors
#16 | 2021-08-26System and method for optimizing system power and performance with high power memory modules
#17 | 2021-08-05System and method for utilizing enhanced thermal telemetry for differential storage of data on a memory module
#18 | 2021-01-14Memory device failure recovery system
#19 | 2020-11-26FLEXIBLE MID-CHASSIS EXTENSION MODULE
#20 | 2020-10-08System and method of rerouting an inter-processor communication link based on a link utilization value
#21 | 2020-08-27System and method to dynamically increase memory channel robustness at high transfer rates
#22 | 2020-08-13System and method of rerouting an inter-processor communication link based on a link utilization value
#23 | 2020-08-04System and method to monitor component wear on high speed serial interfaces
#24 | 2020-07-30Apparatus and method of optimizing memory transactions to persistent memory using an architectural data mover
#25 | 2020-07-16System and method of asymmetric system description for optimized scheduling
#26 | 2020-05-28System and method for providing per channel frequency optimization in a double data rate memory system
#27 | 2020-04-30Method and apparatus to provide platform power peak limiting based on charge of power assist unit
#28 | 2019-11-28System and method of utilizing memory modules
#29 | 2019-09-19System and method to optimize equalization coefficients in a high-speed serial interface
#30 | 2019-09-19System and method for providing per channel frequency optimization in a double data rate memory system
#31 | 2019-08-01Systems and methods for load-balancing cache flushes to non-volatile memory
#32 | 2019-07-25System and method to dynamically increase memory channel robustness at high transfer rates
#33 | 2019-07-25System and method for mapping physical memory with mixed storage class memories
#34 | 2019-04-11SYSTEMS AND METHODS FOR PROVIDING POST-PACKAGE REPAIR VISIBILITY TO A HOST FOR MEMORY RELIABILITY, AVAILABILITY, AND SERVICEABILITY
#35 | 2019-04-11System and method for post-package repair across DRAM banks and bank groups
#36 | 2019-02-07Systems and methods for frequency shifting resonance of an unused via in a printed circuit board
#37 | 2018-12-13System and method for setting equalization for communication between a processor and a device
#38 | 2018-11-08Server display for displaying server component information
#39 | 2018-11-08System and method for setting communication channel equalization of a communication channel between a processing unit and a memory
#40 | 2018-08-30System and method for data restore flexibility on dual channel NVDIMMs
#41 | 2018-08-30System and method for providing predictive failure detection on DDR5 DIMMs using on-die ECC
#42 | 2018-08-16System and method for providing a back door communication path between channels on dual-channel DIMMs
#43 | 2018-08-02Structure to dampen barrel resonance of unused portion of printed circuit board via
#44 | 2018-05-31System and method for communicating over a connector device based on component characteristics stored with the components of the connector device
#45 | 2018-05-31System and method for device assembly based on component characteristics stored with the components
#46 | 2018-03-29Lossy Drain Wire on a High Speed Cable
#47 | 2018-03-29System level crosstalk mitigation
#48 | 2018-03-27System and method for jitter negation in a high speed serial interface
#49 | 2018-02-22Storage class memory (SCM) memory mode cache system
#50 | 2018-02-01Configurable multi-rail voltage regulation with coupled inductor power steering
#51 | 2018-02-01System and method for controlling cache flush size
#52 | 2017-12-14Repeatable backchannel link adaptation for high speed serial interfaces
#53 | 2017-11-21System and method for optimizing link performance with lanes operating at different speeds
#54 | 2017-11-02System and method for performance optimal partial rank/bank interleaving for non-symmetrically populated DIMMs across DDR channels
#55 | 2017-10-12System and method for providing kernel intrusion prevention and notification
#56 | 2017-10-05Storage class memory (SCM) memory mode cache system
#57 | 2017-09-26System and method of read/write control for dual channel memory modules for robust performance
#58 | 2017-08-10Systems and methods for providing grooved vias in high-speed printed circuit boards
#59 | 2017-08-10System aware transmitter adaptation for high speed serial interfaces
#60 | 2017-08-08System and method of training optimization for dual channel memory modules
#61 | 2017-08-03Systems and methods for management controller enhanced power supply unit current sharing
#62 | 2017-05-25Systems and methods for a multi-rail voltage regulator with configurable phase allocation
#63 | 2017-05-11System and method of transferring data over available pins
#64 | 2017-05-04Dynamic power budget allocation
#65 | 2017-04-13System and method to proactively screen component wear through time domain response profiling
#66 | 2017-04-04Systems and methods for automatic detection and configuration of voltage regulator phases in a multi-rail voltage regulator
#67 | 2017-03-30System and method of selective encoding for enhanced serializer/deserializer throughput
#68 | 2017-03-30System and method to blacklist equalization coefficients in a high-speed serial interface
#69 | 2017-03-23Power aware receiver/transmitter adaptation for high speed serial interfaces
#70 | 2017-03-09Systems and methods for virtual current sharing between a power supply unit and a battery back-up unit
#71 | 2017-03-02Systems and methods for hidden battery cell charging and conditioning
#72 | 2017-03-02Information handling system with persistent memory and alternate persistent memory
#73 | 2017-02-23Systems and methods to optimize boot for information handling system comprising persistent memory
#74 | 2017-02-23Systems and methods for real-time cache flush measurements in an information handling system
#75 | 2017-02-23System and method for reducing power consumption of memory
#76 | 2017-01-19Methods of power supply unit rotating in an information handling system
#77 | 2016-11-03Systems and methods for data alignment in a memory system
#78 | 2016-08-16Systems and methods for data alignment in a memory system
#79 | 2016-07-21System aware transmitter adaptation for high speed serial interfaces
#80 | 2016-06-23System and method for providing kernel intrusion prevention and notification
#81 | 2016-06-23System and method for performance optimal partial rank/bank interleaving for non-symmetrically populated DIMMs across DDR channels
#82 | 2016-05-26Systems and methods for extension of power supply hold-up time
#83 | 2016-05-12Repeatable backchannel link adaptation for high speed serial interfaces
#84 | 2016-05-12Systems and methods for support of non-volatile memory on a DDR memory channel
#85 | 2016-04-14Power aware receiver/transmitter adaptation for high speed serial interfaces
#86 | 2016-04-12System aware transmitter adaptation for high speed serial interfaces
#87 | 2016-03-17Information handling system heat sink compatibility management
#88 | 2016-03-10Power management system
#89 | 2016-03-03System and method for simulating a memory technology
#90 | 2016-01-14System and method for enabling transportability of a non volatile dual inline memory module
#91 | 2015-12-24Systems and methods for temperature-based performance optimization of memory devices
#92 | 2015-12-17Systems and methods for distinguishing information handling system provider-supported information handling resource via system license
#93 | 2015-08-13Supplemental power system for power excursions
#94 | 2015-07-30Structure to dampen barrel resonance of unused portion of printed circuit board via
#95 | 2015-07-30Systems and methods for frequency shifting resonance of an unused via in a printed circuit board
#96 | 2015-02-12Adjustable heat sink supporting multiple platforms and system configurations
#97 | 2014-12-25Date adjusted power budgeting for an information handling system
#98 | 2014-12-04Secure original equipment manufacturer (OEM) identifier for OEM devices
#99 | 2014-12-04Verifying OEM components within an information handling system using original equipment manufacturer (OEM) identifier
#100 | 2014-08-28Systems and methods for impedance matching for multi-drop topologies
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