David S. Levitan

Selectively supporting static branch prediction settings only in association with processor-designated types of instructions

Variable latency flush filtering

Instruction prefetching in a computer processor using a prefetch prediction vector

Dynamic sequential instruction prefetching

Power management of branch predictors in a computer processor

ADMINISTERING INSTRUCTION TAGS IN A COMPUTER PROCESSOR

Managing an effective address table in a multi-slice processor

Generating a mask vector for determining a processor instruction address using an instruction tag in a multi-slice processor

Managing an effective address table in a multi-slice processor

Power management of branch predictors in a computer processor

Power management of branch predictors in a computer processor

Operation of a multi-slice processor implementing tagged geometric history length (TAGE) branch prediction

Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor

HAZARD AVOIDANCE IN A MULTI-SLICE PROCESSOR

Techniques for dynamic sequential instruction prefetching

HAZARD AVOIDANCE IN A MULTI-SLICE PROCESSOR

Techniques for predicting a target address of an indirect branch instruction

TECHNIQUES FOR RESTORING PREVIOUS VALUES TO REGISTERS OF A PROCESSOR REGISTER FILE

Instruction prefetching in a computer processor using a prefetch prediction vector

Blocking instruction fetching in a computer processor

Branch prediction in a computer processor

Branch prediction using multiple versions of history data

Branch prediction using multiple versions of history data

Branch prediction using multiple versions of history data

Predicting indirect branches using problem branch filtering and pattern cache

Branch prediction using multiple versions of history data

Compressed indirect prediction caches

Tracking long GHV in high performance out-of-order superscalar processors

Identifying and tagging breakpoint instructions for facilitation of software debug

Identifying and tagging breakpoint instructions for facilitation of software debug

Hardware-assisted program trace collection with selectable call-signature capture

Reducing store-hit-loads in an out-of-order processor

HARDWARE-ASSISTED PROGRAM TRACE COLLECTION WITH SELECTABLE CALL-SIGNATURE CAPTURE

Task switch immunized performance monitoring

Controlling power of a cache based on predicting the instruction cache way for high power applications

Hardware Assist for Optimizing Code During Processing

Operating a stack of information in an information handling system

Saving power by powering down an instruction fetch array based on capacity history of instruction buffer

Tracking effective addresses in an out-of-order processor

METHOD AND APPARATUS FOR OPTIMIZED METHOD OF BHT BANKING AND MULTIPLE UPDATES

Branch target address cache with hashed indices

Branch prediction with partially folded global history vector for reduced XOR operation time

Branch target address cache selectively applying a delayed hit

Branch target address cache storing direct predictions

Branch target address cache including address type tag bit

Branch target address cache

Method for resource balancing using dispatch flush in a simultaneous multithread processor

System and method for optimizing branch logic for handling hard to predict indirect branches

SYSTEM AND STRUCTURE FOR SYNCHRONIZED THREAD PRIORITY SELECTION IN A DEEPLY PIPELINED MULTITHREADED MICROPROCESSOR

Apparatus and computer program product for testing ability to recover from cache directory errors

Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache