Austin, Texas
United States
55
2025-01-30
The entities that hold a legal rights for patent applications filed by inventor Cho Minsik:
Minsik Cho from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MEMORY-EFFICIENT DIFFERENTIABLE WEIGHT CLUSTERING FOR LARGE LANGUAGE MODEL COMPRESSION
#2 | 2023-10-26Mirroring matrices for batched cholesky decomposition on a graphic processing unit
#3 | 2023-03-02Large model support in deep learning
#4 | 2022-12-29SENSOR COMPENSATION USING BACKPROPAGATION
#5 | 2021-08-26System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unit
#6 | 2021-05-20ISA-based compression in distributed training of neural networks
#7 | 2021-03-11TRANSFER LEARNING WITH AUGMENTED NEURAL NETWORKS
#8 | 2020-11-19Method to measure similarity of datasets for given AI task
#9 | 2020-11-19Hamming distance based robust output encoding for improved generalization
#10 | 2020-11-19Separating public and private knowledge in AI
#11 | 2020-10-01Cloud computing data compression for allreduce in deep learning
#12 | 2020-10-01Matrix-factorization based gradient compression
#13 | 2020-10-01Method for flexible, fast all-reduce on arbitrary tree topology
#14 | 2020-08-06Pessimistic scheduling for topology optimized workload placement
#15 | 2020-07-09Pipelining multi-directional reduction
#16 | 2020-06-04Decentralized distributed deep learning
#17 | 2020-05-07Large model support in deep learning
#18 | 2020-02-20System, method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit
#19 | 2019-09-26System, Method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit
#20 | 2019-04-18System, method and computer program product for accelerating iterative graph algorithms by memory layout optimization
#21 | 2019-03-21Variable ISA vector-based compaction in distributed training of neural networks
#22 | 2019-03-21ISA-based compression in distributed training of neural networks
#23 | 2018-12-13Multi-directional reduction in large scale deep-learning
#24 | 2018-12-13Parallel quicksort
#25 | 2018-08-02Memory efficient convolution operations in deep learning neural networks
#26 | 2018-08-02System, method and computer program product for accelerating iterative graph algorithms by memory layout optimization
#27 | 2018-07-12System, method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit
#28 | 2018-05-24Radix sort acceleration using custom asic
#29 | 2018-05-03Parallelized in-place radix sorting
#30 | 2018-01-04System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unit
#31 | 2017-10-05LLVM-based system C compiler for architecture synthesis
#32 | 2017-03-30Adaptive radix external in-place radix sort
#33 | 2017-03-23Condition analysis
#34 | 2017-02-23Parallel quicksort
#35 | 2017-01-19In-cycle resource sharing for high-level synthesis of microprocessors
#36 | 2016-12-01Automating a microarchitecture design exploration environment
#37 | 2016-11-29Automating a microarchitecture design exploration environment
#38 | 2016-08-02Automating a microarchitecture design exploration environment
#39 | 2016-06-09Lookup table sharing for memory-based computing
#40 | 2016-06-02Lookup table sharing for memory-based computing
#41 | 2015-10-22Parallelized in-place radix sorting
#42 | 2015-10-22Parallelized in-place radix sorting
#43 | 2015-10-15Radix sort acceleration using custom ASIC
#44 | 2015-07-30Parallelized in-place radix sorting
#45 | 2015-07-30Parallelized in-place radix sorting
#46 | 2015-07-30Radix sort acceleration using custom ASIC
#47 | 2015-02-19Mapping a lookup table to prefabricated TCAMS
#48 | 2015-01-01Lookup table sharing for memory-based computing
#49 | 2015-01-01Lookup table sharing for memory-based computing
#50 | 2013-12-05Structured Latch and Local-Clock-Buffer Planning
#51 | 2013-10-03Relative ordering circuit synthesis
#52 | 2013-07-23Structured latch and local-clock-buffer planning
#53 | 2013-05-23Network flow based datapath bit slicing
#54 | 2013-02-28Soft hierarchy-based physical synthesis for large-scale, high-performance circuits
#55 | 2009-01-29Method and system for performing global routing on an integrated circuit design
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