Murphy, Texas
United States
24
2024-11-21
The entities that hold a legal rights for patent applications filed by inventor Tran Jonathan (Son) Hung:
Jonathan (Son) Hung Tran from Murphy, US has applied for patents for these inventions. The list has both pending applications and granted patents:
CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE
#2 | 2024-11-07STORAGE ORGANIZATION FOR TRANSPOSING A MATRIX USING A STREAMING ENGINE
#3 | 2024-06-06MECHANISM TO QUEUE MULTIPLE STREAMS TO RUN ON STREAMING ENGINE
#4 | 2022-08-04Cache Preload Operations Using Streaming Engine
#5 | 2021-12-30Cache management operations using streaming engine
#6 | 2021-07-22Mechanism to queue multiple streams to run on streaming engine
#7 | 2021-06-24Storage organization for transposing a matrix using a streaming engine
#8 | 2020-09-10Cache preload operations using streaming engine
#9 | 2020-09-10Cache management operations using streaming engine
#10 | 2019-06-27Mechanism to queue multiple streams to run on streaming engine
#11 | 2019-06-20Transposing a matrix using a streaming engine
#12 | 2019-06-20Storage organization for transposing a matrix using a streaming engine
#13 | 2019-03-28Cache preload operations using streaming engine
#14 | 2019-03-28Cache management operations using streaming engine
#15 | 2016-06-30Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors
#16 | 2015-09-24Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty
#17 | 2015-06-25Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence
#18 | 2012-08-02Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines
#19 | 2012-08-02Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence
#20 | 2012-08-02Hazard prevention for data conflicts between level one data cache line allocates and snoop writes
#21 | 2012-07-26Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme
#22 | 2012-07-26Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers
#23 | 2012-07-26Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty
#24 | 2012-03-29Cache with multiple access pipelines
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