Schenectady, New York
United States
20
2022-04-28
The entities that hold a legal rights for patent applications filed by inventor BASKER Veeraraghavan:
Veeraraghavan BASKER from Schenectady, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Vertical transistor including symmetrical source/drain extension junctions
#2 | 2022-04-07Partial self-aligned contact for MOL
#3 | 2021-08-26Vertical transistor including symmetrical source/drain extension junctions
#4 | 2021-08-12Nanosheet transistor having partially self-limiting bottom isolation extending into the substrate and under the source/drain and gate regions
#5 | 2021-05-06Partial self-aligned contact for MOL
#6 | 2021-04-15Replacement gate cross-couple for static random-access memory scaling
#7 | 2020-11-19Nanosheet bottom isolation and source or drain epitaxial growth
#8 | 2020-10-22Contact interlayer dielectric replacement with improved SAC cap retention
#9 | 2020-04-30Gate contact over active enabled by alternative spacer scheme and claw-shaped cap
#10 | 2020-01-16Contact structures for integrated circuit products
#11 | 2019-06-13Methods of forming contact structures on integrated circuit products
#12 | 2018-02-15Self-aligned punch through stopper liner for bulk FinFET
#13 | 2017-03-16Self-aligned punch through stopper liner for bulk FinFET
#14 | 2017-03-09Self-aligned punch through stopper liner for bulk FinFET
#15 | 2017-01-31Self-aligned punch through stopper liner for bulk FinFET
#16 | 2016-12-22Method of source/drain height control in dual epi finFET formation
#17 | 2016-06-28Method of forming source/drain contacts in unmerged FinFETs
#18 | 2016-06-21Integrated FinFET capacitor
#19 | 2016-05-10Integrated FinFET capacitor
#20 | 2015-06-25Buried local interconnect in finfet structure and method of fabricating same
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