Inventor profile of:

Nigel John Stephens

City:

Cambridge

Country:

United Kingdom

Published Applications:

30

Last publication date:

2025-05-29

Top Assignees for applications by Nigel John Stephens

The entities that hold a legal rights for patent applications filed by inventor Stephens Nigel John:

Recent patent applications by Stephens Nigel John

Nigel John Stephens from Cambridge, GB has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-05-29
US20250173146A1
Physics

TECHNIQUE FOR HANDLING DATA ELEMENTS STORED IN AN ARRAY STORAGE

#2 | 2024-10-24
US20240354105A1
Physics

APPARATUS AND METHOD FOR PERFORMING A SPLICE OPERATION

#3 | 2023-09-14
US20230289186A1
Physics

Register addressing information for data transfer instruction

#4 | 2023-08-31
US20230273792A1
Physics

Processing instructions selected from a first instruction set in a first processing mode and instructions selected from a second different instruction set in a second processing mode

#5 | 2021-02-11
US20210042261A1
Physics

Data processing

#6 | 2021-02-11
US20210042115A1
Physics

Data structure processing

#7 | 2021-02-11
US20210042114A1
Physics

Data structure relinquishing

#8 | 2021-02-04
US20210034362A1
Physics

Data processing

#9 | 2021-01-28
US20210026629A1
Physics

Vector interleaving in a data processing apparatus

#10 | 2020-10-08
US20200319885A1
Physics

Vector add-with-carry instruction

#11 | 2020-08-06
US20200249942A1
Physics

Anchored data element conversion

#12 | 2020-07-16
US20200225953A1
Physics

Testing bit values inside vector elements

#13 | 2019-12-12
US20190377573A1
Physics

Element by vector operations in a data processing apparatus

#14 | 2019-06-06
US20190171376A1
Physics

Handling contingent and non-contingent memory access program instructions making use of disable flag

#15 | 2019-03-21
US20190088307A1
Physics

Bit processing

#16 | 2019-01-24
US20190026173A1
Physics

Vector atomic memory update instruction

#17 | 2019-01-10
US20190012176A1
Physics

Vector processing using loops of dynamic vector length

#18 | 2018-10-11
US20180293078A1
Physics

Handling exceptional conditions for vector arithmetic instruction

#19 | 2018-09-20
US20180267798A1
Physics

Determine whether to fuse move prefix instruction and immediately following instruction independently of detecting identical destination registers

#20 | 2018-09-06
US20180253310A1
Physics

Vector load instruction

#21 | 2018-09-06
US20180253309A1
Physics

Vector data transfer instruction

#22 | 2018-07-26
US20180210733A1
Physics

Apparatus and method for performing a splice of vectors based on location and length data

#23 | 2018-07-26
US20180210731A1
Physics

Propagation instruction to generate a set of predicate flags based on previous and current prediction data

#24 | 2018-07-19
US20180203756A1
Physics

Contingent load suppression

#25 | 2018-07-19
US20180203699A1
Physics

Vector operand bitsize control

#26 | 2018-07-12
US20180196673A1
Physics

Vector length querying instruction

#27 | 2017-11-16
US20170329603A1
Physics

Conditional selection of data elements

#28 | 2017-02-02
US20170031865A1
Physics

Apparatus and method for transferring a plurality of data structures between memory and a plurality of vector registers

#29 | 2015-07-02
US20150186142A1
Physics

MIXED SIZE DATA PROCESSING OPERATION

#30 | 2012-09-13
US20120233444A1
Physics

Mixed operand size instruction processing for execution of indirect addressing load instruction specifying registers for different size operands

InventorID:

1214701 ⎘