Daniel Mark Dreps

CLOCK SYNCHRONIZATION IN A MULTICHIP MODULE

TWO-STAGE PROCESSOR VOLTAGE REGULATION

MULTI-PHASE CLOCK GENERATION CIRCUIT WITH DIGITAL CALIBRATION

Active Inductor Peaking Buffer with Output Common Mode Control

PROCESSOR PACKAGE SUBSTRATE WITH HIGH-SPEED TOP-SURFACE CONNECTION TO CABLE INTERCONNECT

DENSE VIA PITCH INTERCONNECT TO INCREASE WIRING DENSITY

Calibrating a quadrature receive serial interface

Dense via pitch interconnect to increase wiring density

Communication systems for power supply noise reduction

Communication systems for power supply noise reduction

Quadrature circuit interconnect architecture with clock forwarding

REAL-TIME CONTROL OF VIA STUB DRILLING DEPTH ASYMMETRY

Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output

System interconnect dynamic scaling by predicting I/O requirements

Bus interface optimization by selecting bit-lanes having best performance margins

Bus interface optimization by selecting bit-lanes having best performance margins

Variable voltage CMOS off-chip driver and receiver circuits

Self-healing chip-to-chip interface

Self-healing chip-to-chip interface

Method for performing memory diagnostics using a programmable diagnostic memory module

Programmable diagnostic memory module

System for reducing cross-talk induced source synchronous bus clock jitter

Architecture for a physical interface of a high speed front side bus

Architecture for a physical interface of a high speed front side bus

Method for reducing cross-talk induced source synchronous bus clock jitter

Implementing phase rotator circuits with embedded polyphase filter network stage

Self-healing chip-to-chip interface

Self-healing chip-to-chip interface

Data processing system and method with dynamic idle for tunable interface calibration

Digitally tunable high-current current reference with high PSRR

Adjustable switchpoint receiver

Method and apparatus for interface signaling using single-ended and differential data signals

Comparator and method for detecting a signal using a reference derived from a differential data signal pair

Modable dynamic terminator for high speed digital communications

Method and apparatus for supplying a reference voltage for chip-to-chip communication