Caldwell, Idaho
United States
25
2026-03-26
The entities that hold a legal rights for patent applications filed by inventor Gambee Christopher J.:
Christopher J. Gambee from Caldwell, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Memory Circuitry And Methods Used In Forming Memory Circuitry
#2 | 2020-11-26Die features for self-alignment during die bonding
#3 | 2020-11-19Devices with three-dimensional structures and support elements to increase adhesion to substrates
#4 | 2020-07-30Reduction of roughness on a sidewall of an opening
#5 | 2020-03-12Die features for self-alignment during die bonding
#6 | 2019-12-26Methods for enhancing adhesion of three-dimensional structures to substrates
#7 | 2019-11-07Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography
#8 | 2019-08-22Methods of fabricating conductive traces and resulting structures
#9 | 2019-06-20Semiconductor devices having discretely located passivation material, and associated systems and methods
#10 | 2019-06-20Methods of fabricating conductive traces and resulting structures
#11 | 2019-03-21Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography
#12 | 2019-02-14Semiconductor devices having discretely located passivation material, and associated systems and methods
#13 | 2018-06-19Semiconductor devices having discretely located passivation material, and associated systems and methods
#14 | 2017-10-05Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
#15 | 2016-06-16Semiconductor devices and methods for backside photo alignment
#16 | 2015-11-19Semiconductor devices and methods for backside photo alignment
#17 | 2015-07-30Semiconductor structures comprising at least one through-substrate via filled with conductive materials
#18 | 2015-05-21Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
#19 | 2014-06-19Pillar on pad interconnect structures, semiconductor devices including same and related methods
#20 | 2014-06-12Methods of selectively removing a substrate material
#21 | 2014-01-16Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods
#22 | 2013-01-03Methods of forming a metal pattern
#23 | 2011-09-01Methods of forming a metal pattern and semiconductor device structure
#24 | 2008-10-09Method to create a metal pattern using a damascene-like process
#25 | 2006-11-09Intermediate semiconductor device structures
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