Inventor profile of:

Serag GadelRab

City:

Markham

Country:

Canada

Published Applications:

21

Last publication date:

2025-06-05

Top Assignees for applications by Serag GadelRab

The entities that hold a legal rights for patent applications filed by inventor GadelRab Serag:

Recent patent applications by GadelRab Serag

Serag GadelRab from Markham, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-06-05
US20250181978A1
Physics

CONCURRENT OPTIMIZATION OF MACHINE LEARNING MODEL PERFORMANCE

#2 | 2024-04-04
US20240112090A1
Physics

Concurrent optimization of machine learning model performance

#3 | 2021-09-16
US20210288660A1
Electricity

Compression of high dynamic ratio fields for machine learning

#4 | 2021-09-09
US20210279635A1
Physics

Adaptive quantization for execution of machine learning models

#5 | 2021-01-21
US20210019652A1
Physics

Concurrent optimization of machine learning model performance

#6 | 2020-08-27
US20200274549A1
Electricity

Compression of high dynamic ratio fields for machine learning

#7 | 2020-06-18
US20200195977A1
Electricity

SYSTEM AND METHOD FOR INTELLIGENT DATA/FRAME COMPRESSION IN A SYSTEM ON A CHIP

#8 | 2020-03-19
US20200092564A1
Electricity

System and method for foveated compression of image frames in a system on a chip

#9 | 2019-04-11
US20190110053A1
Electricity

System and method for foveated compression of image frames in a system on a chip

#10 | 2018-10-18
US20180302625A1
Electricity

System and method for intelligent data/frame compression in a system on a chip

#11 | 2018-10-18
US20180302624A1
Electricity

System and method for intelligent data/frame compression in a system on a chip

#12 | 2018-09-06
US20180253236A1
Physics

System and method for dynamic control of shared memory management resources

#13 | 2018-06-14
US20180165789A1
Physics

Fetch reduction for fixed color and pattern sub-frames

#14 | 2017-08-10
US20170228252A1
Physics

SYSTEM AND METHOD FOR MULTI-TILE DATA TRANSACTIONS IN A SYSTEM ON A CHIP

#15 | 2017-03-23
US20170083262A1
Physics

System and method for controlling memory frequency using feed-forward compression statistics

#16 | 2017-01-26
US20170024145A1
Physics

ADDRESS TRANSLATION AND DATA PRE-FETCH IN A CACHE MEMORY SYSTEM

#17 | 2016-12-01
US20160350225A1
Physics

Speculative pre-fetch of translations for a memory management unit (MMU)

#18 | 2016-09-29
US20160283384A1
Physics

Command-driven translation pre-fetch for memory management units

#19 | 2015-08-20
US20150234761A1
Physics

ARBITRATING BUS TRANSACTIONS ON A COMMUNICATIONS BUS BASED ON BUS DEVICE HEALTH INFORMATION AND RELATED POWER MANAGEMENT

#20 | 2011-06-23
US20110150085A1
Electricity

Temporal and spatial video block reordering in a decoder to improve cache hits

#21 | 2008-10-02
US20080240111A1
Electricity

Method and apparatus for writing network packets into computer memory

InventorID:

1264277 ⎘