Austin, Texas
United States
52
2023-07-27
The entities that hold a legal rights for patent applications filed by inventor Mealey Bruce:
Bruce Mealey from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Accelerator access control
#2 | 2020-03-19Accelerator access control
#3 | 2020-03-05Shared and exclusive accelerator access
#4 | 2019-12-12Use of capi-attached storage as extended memory
#5 | 2018-08-30Dynamic virtual processor manager
#6 | 2018-05-10Off-line affinity-aware parallel zeroing of memory in non-uniform memory access (NUMA) servers
#7 | 2018-05-03Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core
#8 | 2018-04-12Efficient critical thread scheduling for non-privileged thread requests
#9 | 2018-03-29Affinity-aware parallel zeroing of memory for initialization of large pages in non-uniform memory access (NUMA) servers
#10 | 2018-03-29Affinity aware parallel zeroing of memory in non-uniform memory access (NUMA) servers
#11 | 2018-03-22Efficient critical thread scheduling for non privileged thread requests
#12 | 2017-05-25Dynamic virtual processor manager
#13 | 2017-05-18Techniques for escalating interrupts in a data processing system to a higher software stack level
#14 | 2017-05-11Enabling poll/select style interfaces with coherent accelerators
#15 | 2017-05-11Resolving page faults out of context
#16 | 2017-05-11Enabling poll/select style interfaces with coherent accelerators
#17 | 2017-05-04Resolving page faults out of context for shared contexts
#18 | 2017-05-04Emulating memory mapped I/O for coherent accelerators in error state
#19 | 2017-04-27Sharing an accelerator context across multiple processes
#20 | 2017-04-27Low latency scheduling on simultaneous multi-threading cores
#21 | 2017-04-27Low latency scheduling on simultaneous multi-threading cores
#22 | 2017-04-27Sharing an accelerator context across multiple processes
#23 | 2017-04-20Affinity-aware parallel zeroing of memory for initialization of large pages in non-uniform memory access (NUMA) servers
#24 | 2016-12-29Affinity-aware parallel zeroing of memory in non-uniform memory access (NUMA) servers
#25 | 2016-12-29Off-line affinity-aware parallel zeroing of memory in non-uniform memory access (NUMA) servers
#26 | 2016-12-29Affinity-aware parallel zeroing of pages in non-uniform memory access (NUMA) servers
#27 | 2016-12-29Affinity-aware parallel zeroing of memory for initialization of large pages in non-uniform memory access (NUMA) servers
#28 | 2016-12-01Efficient critical thread scheduling for non-privileged thread requests
#29 | 2016-12-01Efficient critical thread scheduling for non-privileged thread requests
#30 | 2015-09-10Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core
#31 | 2014-09-18Memory page de-duplication in a computer system that includes a plurality of virtual machines
#32 | 2014-09-18Memory page de-duplication in a computer system that includes a plurality of virtual machines
#33 | 2012-08-16Dual mode reader writer lock
#34 | 2012-05-31Global and local counts for efficient memory page pinning in a multiprocessor system
#35 | 2012-03-15Using a dual mode reader writer lock
#36 | 2011-09-15Dual mode reader writer lock
#37 | 2011-09-15Retooling lock interfaces for using a dual mode reader writer lock
#38 | 2011-09-15Using a dual mode reader writer lock
#39 | 2011-01-27Software component self-scrubbing
#40 | 2010-05-06Controlling priority of multi-threaded hardware resources by system calls
#41 | 2008-10-23Key-controlled object-based memory protection
#42 | 2008-08-21Recovery routine masking and barriers to support phased recovery development
#43 | 2008-08-21Kernel error recovery disablement and shared recovery routine footprint areas
#44 | 2008-07-10Key-controlled object-based memory protection
#45 | 2008-07-10Detecting illegal reuse of memory with low resource impact
#46 | 2007-11-22Scaling address space utilization in a multi-threaded, multi-processor computer
#47 | 2006-05-11Method, system, and program for transferring data directed to virtual memory addresses to a device memory
#48 | 2006-04-04Virtual logical partition terminal
#49 | 2006-03-09Scaling address space utilization in a multi-threaded, multi-processor computer
#50 | 2006-02-16Key-controlled object-based memory protection
#51 | 2005-10-04Method and system for system performance optimization via heuristically optimized buses
#52 | 2005-08-16Method, apparatus, and computer program product for migrating data subject to access by input/output devices
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