Cold Spring, New York
United States
40
2019-07-04
The entities that hold a legal rights for patent applications filed by inventor FEE Michael F.:
Michael F. FEE from Cold Spring, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Configuration based cache coherency protocol selection
#2 | 2018-05-03Configuration based cache coherency protocol selection
#3 | 2018-05-03Configuration based cache coherency protocol selection
#4 | 2016-12-08Dynamic cache row fail accumulation due to catastrophic failure
#5 | 2016-08-18Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing
#6 | 2016-08-18Position-based replacement policy for address synonym management in shared caches
#7 | 2016-08-18Dynamic cache row fail accumulation due to catastrophic failure
#8 | 2016-08-18Dynamic cache row fail accumulation due to catastrophic failure
#9 | 2016-05-26Dynamic partial blocking of a cache ECC bypass
#10 | 2016-05-26Configuration based cache coherency protocol selection
#11 | 2016-05-26Configuration based cache coherency protocol selection
#12 | 2016-05-26Dynamic partial blocking of a cache ECC bypass
#13 | 2016-05-19Memory controlled operations under dynamic relocation of storage
#14 | 2015-12-31Mitigating busy time in a high performance cache
#15 | 2015-09-17Managing quiesce requests in a multi-processor environment
#16 | 2015-08-11Managing quiesce requests in a multi-processor environment
#17 | 2014-04-03Cross-pipe serialization for multi-pipeline processor
#18 | 2014-04-03Reducing penalties for cache accessing operations
#19 | 2013-12-19Cross-pipe serialization for multi-pipeline processor
#20 | 2013-12-19Reducing store operation busy times
#21 | 2013-12-19Reducing store operation busy times
#22 | 2013-12-19Reducing penalties for cache accessing operations
#23 | 2013-03-28Dynamic mode transitions for cache instructions
#24 | 2013-03-28Managing in-line store throughput reduction
#25 | 2013-03-07Mitigating busy time in a high performance cache
#26 | 2011-12-29Tracking dynamic memory reallocation using a single storage address configuration table
#27 | 2011-12-29Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy
#28 | 2011-12-29Dynamic mode transitions for cache instructions
#29 | 2011-12-29Management of multipurpose command queues in a multilevel cache hierarchy
#30 | 2011-12-29Dynamically supporting variable cache array busy and access times for a targeted interleave
#31 | 2011-12-29Mitigating busy time in a high performance cache
#32 | 2011-12-29System, apparatus and method utilizing early access to shared cache pipeline for latency reduction
#33 | 2011-12-22Managing in-line store throughput reduction
#34 | 2011-12-22Recover store data merging
#35 | 2011-06-09Updating settings of a processor core concurrently to the operation of a multi core processor system
#36 | 2009-09-24Method, system and computer program product for data buffers partitioned from a cache array
#37 | 2009-08-27Least recently used (LRU) compartment capture in a cache memory system
#38 | 2009-08-27Method, system, and computer program product for pipeline arbitration
#39 | 2009-08-27System, method and computer program product for providing a new quiesce state
#40 | 2009-03-26System to Improve Data Store Throughput for a Shared-Cache of a Multiprocessor Structure and Associated Methods
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