Palo Alto, California
United States
27
2021-09-30
The entities that hold a legal rights for patent applications filed by inventor Grupp Daniel E.:
Daniel E. Grupp from Palo Alto, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#2 | 2020-08-27Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#3 | 2020-08-27Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#4 | 2020-07-30Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#5 | 2019-10-31Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#6 | 2018-09-20Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#7 | 2018-06-14Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#8 | 2018-02-01Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#9 | 2016-12-22Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#10 | 2016-06-16Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#11 | 2016-06-16Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#12 | 2015-10-08Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#13 | 2012-11-08Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#14 | 2011-09-01Insulated gate field effect transistor having passivated schottky barriers to the channel
#15 | 2011-07-14Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#16 | 2011-05-26Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
#17 | 2011-01-13Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)
#18 | 2009-04-23Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#19 | 2007-09-27Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)
#20 | 2007-02-01Insulated gate field effect transistor having passivated schottky barriers to the channel
#21 | 2006-09-26Insulated gate field effect transistor having passivated Schottky barriers to the channel
#22 | 2006-08-01Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#23 | 2006-04-20Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
#24 | 2005-11-10Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#25 | 2005-05-19Insulated gate field-effect transistor having III-VI source/drain layer(s)
#26 | 2005-05-10Transistor with workfunction-induced charge layer
#27 | 2005-05-05Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
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