Inventor profile of:

John D. Davis

City:

Maybrook, New York

Country:

United States

Published Applications:

19

Last publication date:

2018-12-20

Top Assignees for applications by John D. Davis

The entities that hold a legal rights for patent applications filed by inventor Davis John D.:

Recent patent applications by Davis John D.

John D. Davis from Maybrook, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-12-20
US20180367145A1
Electricity

Dynamic decode circuit with active glitch control

#2 | 2018-11-08
US20180323787A1
Electricity

Dynamic decode circuit with delayed precharge

#3 | 2018-11-08
US20180323786A1
Electricity

Dynamic decode circuit with active glitch control method

#4 | 2018-11-01
US20180316354A1
Electricity

Dynamic decode circuit with active glitch control method

#5 | 2018-03-29
US20180091153A1
Electricity

Dynamic decode circuit with active glitch control

#6 | 2018-03-29
US20180091152A1
Electricity

Dynamic decode circuit with active glitch control

#7 | 2018-01-04
US20180005674A1
Physics

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

#8 | 2017-08-24
US20170243619A1
Physics

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

#9 | 2017-08-22
US15274322
Electricity

Dynamic decode circuit with active glitch control

#10 | 2015-10-22
US20150302908A1
Physics

Write/read priority blocking scheme using parallel static address decode path

#11 | 2015-10-22
US20150302902A1
Physics

Write/read priority blocking scheme using parallel static address decode path

#12 | 2015-06-30
US14203790
Physics

SRAM supply voltage global bitline precharge pulse

#13 | 2011-12-29
US20110320851A1
Physics

Port enable signal generation for gating a memory array device output

#14 | 2011-12-29
US20110317505A1
Physics

Internal bypassing of memory array devices

#15 | 2011-12-29
US20110317499A1
Physics

Split voltage level restore and evaluate clock signals for memory address decoding

#16 | 2011-12-29
US20110317496A1
Physics

Jam latch for latching memory array output data

#17 | 2011-12-15
US20110304370A1
Electricity

Programmable control clock circuit including scan mode

#18 | 2007-04-24
US10413612
-

Integrated system logic and ABIST data compression for an SRAM directory

#19 | 2006-07-04
US10413614
-

ABIST address generation

InventorID:

1333525 ⎘