Albert Ratnakumar

Apparatus and associated methods for capacitors with improved density and matching

Methods for fabricating PNP bipolar junction transistors

Integrated Circuits with Asymmetric and Stacked Transistors

Programmable device with a metal oxide semiconductor field effect transistor

Method of fabricating integrated circuit transistors with multipart gate conductors

Integrated circuits with asymmetric and stacked transistors

Method of using a PMOS pass gate

High resolution capacitor

Integrated circuits with asymmetric pass transistors

Integrated circuit resistors with reduced parasitic capacitance

PMOS pass gate

Integrated circuits with asymmetric and stacked transistors

Memory element transistors with reversed-workfunction gate conductors

Integrated circuits with asymmetric and stacked transistors

Integrated circuits with nonvolatile memory elements

Very low voltage reference circuit

Mixed-gate metal-oxide-semiconductor varactors

Integrated circuits with asymmetric pass transistors

Stressed transistors with reduced leakage

Integrated circuits with nonvolatile memory elements

Memory elements with body bias control

Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layers

Integrated circuit transistors with multipart gate conductors

ASYMMETRIC METAL-OXIDE-SEMICONDUCTOR TRANSISTORS

METAL-OXIDE-METAL CAPACITORS WITH BAR VIAS

Process/design methodology to enable high performance logic and analog circuits using a single process

VARACTORS WITH ENHANCED TUNING RANGES