Bruce Joseph Ronchetti

Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices

Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices

Processing of multiple instruction streams in a parallel slice processor

Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices

Reconfigurable parallel execution and load-store slice processor

Processing of multiple instruction streams in a parallel slice processor

Parallel slice processor with dynamic instruction stream mapping

Processing of multiple instruction streams in a parallel slice processor

Parallel slice processor with dynamic instruction stream mapping

Managing instructions for more efficient load/store unit usage

Adaptive data prefetch

Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch

Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream

Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor

Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor

Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch

Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream

Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class