Yi-Ching Liu

FERROELECTRIC MEMORY DEVICE AND METHOD OF MAKING THE SAME

MEMORY PRECHARGE

MEMORY STRUCTURE HAVING NOVEL CIRCUIT ROUTING AND METHOD FOR MANUFACTURING THE SAME

HIGH PERFORMANCE EMBEDDED 1T1C MEMORY CELLS

DRAM COMPUTATION CIRCUIT AND METHOD

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF

USING EMBEDDED SWITCHES FOR REDUCING CAPACITIVE LOADING ON A MEMORY SYSTEM

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF

MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING

THREE-DIMENSIONAL MEMORY DEVICE WITH WORD LINES EXTENDING THROUGH SUB-ARRAYS, SEMICONDUCTOR DEVICE INCLUDING THE SAME AND METHOD FOR MANUFACTURING THE SAME

SWITCHES TO REDUCE ROUTING RAILS OF MEMORY SYSTEM

3D MEMORY ARRAY ARCHETECTURE AND METHOD OF FABRICATING THE SAME

MEMORY CIRCUIT AND METHOD OF OPERATING SAME

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF

BIT LINE DIRECT CHARGE

STRUCTURES OF SRAM CELL AND METHODS OF FABRICATING THE SAME

COMMON-CONNECTION METHOD IN 3D MEMORY

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

MEMORY CIRCUITS, MEMORY STRUCTURES, AND METHODS FOR FABRICATING A MEMORY DEVICE

COMPUTE-IN-MEMORY DEVICE AND METHOD

SWITCHES TO REDUCE ROUTING RAILS OF MEMORY SYSTEM

MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING

DRAM COMPUTATION CIRCUIT AND METHOD

USING EMBEDDED SWITCHES FOR REDUCING CAPACITIVE LOADING ON A MEMORY SYSTEM

USING SPLIT WORD LINES AND SWITCHES FOR REDUCING CAPACITIVE LOADING ON A MEMORY SYSTEM

Memory Array Word Line Routing

Memory circuit and method of operating same

Integrated circuit including three-dimensional memory device

Memory array and operation method thereof

Memory device and method for operating the same

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF

Switches to reduce routing rails of memory system

Memory array connections

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF

Memory including metal rails with balanced loading

MEMORY CIRCUITS

THREE-DIMENSIONAL MEMORY DEVICE WITH WORD LINES EXTENDING THROUGH SUB-ARRAYS, SEMICONDUCTOR DEVICE INCLUDING THE SAME AND METHOD FOR MANUFACTURING THE SAME

Semiconductor memory devices and methods of manufacturing thereof

Memory systems with vertical integration

FERROELECTRIC MEMORY DEVICE AND METHOD OF MAKING THE SAME

MEMORY STRUCTURE HAVING NOVEL CIRCUIT ROUTING AND METHOD FOR MANUFACTURING THE SAME

Reducing capacitive loading of memory system based on switches

Memory systems with vertical integration

Switches to reduce routing rails of memory system

Memory including metal rails with balanced loading

Three-dimensional one time programmable memory

Memory device comprising second memory cell having first terminal coupled to first signal line through first memory cell

DRAM computation circuit and method

Sense amplifier with read circuit for compute-in-memory

Compute-in-memory device and method

Memory circuit and method of operating same

Three-dimensional memory

Memory circuits

Memory circuits, memory structures, and methods for fabricating a memory device

Using split word lines and switches for reducing capacitive loading on a memory system

Memory device

Three dimensional memory device

Memory array word line routing

Semiconductor memory devices and methods of manufacturing thereof

3D memory device with modulated doped channel

Semiconductor memory devices and methods of manufacturing thereof

Semiconductor memory devices with different thicknesses of word lines and methods of manufacturing thereof

Integrated circuit including three-dimensional memory device

Common-connection method in 3D memory

MACHINE PROTECTION FRAME DEVICE WITH FUNCTION OF AIR FILTERING

Using embedded switches for reducing capacitive loading on a memory system

Memory device

Using embedded switches for reducing capacitive loading on a memory system

Three-dimensional memory device with word lines extending through sub-arrays, semiconductor device including the same and method for manufacturing the same

Memory circuit and method of operating same

Memory array word line routing

Performing in-memory computing based on multiply-accumulate operations using non-volatile memory arrays

Boosted voltage driver for bit lines and other circuit nodes

NAND block architecture for in-memory multiply-and-accumulate operations

Memory device and control method thereof

Memory device with programming cycle stages

Memory device and operation method thereof

Boost circuit

Method and circuit for temperature dependence reduction of a RC clock circuit

Boost circuit

Plural operation of memory device

Storage scheme for built-in ECC operations

Plural operation of memory device

Method of programming a nonvolatile memory cell and related memory array

Programming and manufacturing method for split gate memory cell