Jack M. Higman

Three-port memory cell and array for in-memory computing

Dual port static random access memory cell

Dual port static random access memory cell layout

Integrated circuits with edge-adjacent devices having reactance values

Memory with read cycle write back

Integrated circuit memory having assisted access and method therefor

Memory operation testing

Semiconductor device with capacitor and/or inductor and method of making

Memory cells with lower power consumption during a write operation

Two-port SRAM having improved write operation

Primitive cell method for front end physical design

Apparatus and method for adjusting an operating parameter of an integrated circuit

Electronic device and method for operating a memory circuit