Inventor profile of:

Marlin Wayne FREDERICK, JR.

City:

Austin, Texas

Country:

United States

Published Applications:

30

Last publication date:

2026-04-30

Top Assignees for applications by Marlin Wayne FREDERICK, JR.

The entities that hold a legal rights for patent applications filed by inventor FREDERICK, JR. Marlin Wayne:

Recent patent applications by FREDERICK, JR. Marlin Wayne

Marlin Wayne FREDERICK, JR. from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-30
US20260121530A1
Electricity

VOLTAGE STABILIZATION WITH ON-DEVICE METAL CAPACITOR

#2 | 2022-06-16
US20220188496A1
Physics

Cell architecture with backside power rails

#3 | 2022-05-12
US20220147679A1
Physics

Cell architecture with backside power rails

#4 | 2021-06-03
US20210167013A1
Electricity

Power Distribution

#5 | 2021-01-21
US20210019463A1
Physics

Computer implemented system and method for generating a layout of a cell defining a circuit component

#6 | 2020-09-10
US20200286548A1
Physics

Memory structure with bitline strapping

#7 | 2020-04-23
US20200125693A1
Physics

Metal layout techniques

#8 | 2020-01-16
US20200020464A1
Electricity

Power rail stitching technique

#9 | 2019-08-08
US20190244900A1
Electricity

Power distribution circuitry

#10 | 2019-01-24
US20190026417A1
Physics

Computer implemented system and method for generating a layout of a cell defining a circuit component

#11 | 2018-09-25
US15629684
Electricity

Integration fill technique

#12 | 2018-08-09
US20180225402A9
Physics

Computer implemented system and method for generating a layout of a cell defining a circuit component

#13 | 2018-08-02
US20180218108A1
Physics

Sleep signal stitching technique

#14 | 2018-08-02
US20180218107A1
Physics

Power grid healing techniques

#15 | 2018-07-26
US20180211914A1
Electricity

Power distribution

#16 | 2017-06-29
US20170186745A1
Electricity

Resistance mitigation in physical design

#17 | 2017-06-29
US20170185709A1
Physics

Method and apparatus for adjusting a timing derate for static timing analysis

#18 | 2017-03-02
US20170062404A1
Electricity

Via placement within an integrated circuit

#19 | 2016-12-08
US20160357894A1
Physics

Method for adjusting a timing derate for static timing analysis

#20 | 2015-12-24
US20150371959A1
Electricity

Power grid conductor placement within an integrated circuit

#21 | 2015-12-24
US20150370953A1
Physics

Via placement within an integrated circuit

#22 | 2015-12-03
US20150349760A1
Electricity

Data and clock signal voltages within an integrated circuit

#23 | 2015-02-17
US14039224
Physics

Considering compatibility of adjacent boundary regions for standard cells placement and routing

#24 | 2014-04-24
US20140115554A1
Physics

METHOD OF GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT COMPRISING BOTH STANDARD CELLS AND AT LEAST ONE MEMORY INSTANCE

#25 | 2014-02-04
US13658072
-

Method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance

#26 | 2013-03-14
US20130064019A1
Physics

Data storage circuit that retains state during precharge

#27 | 2012-11-15
US20120286824A1
Electricity

Supplying a clock signal and a gated clock signal to synchronous elements

#28 | 2012-01-19
US20120013319A1
Physics

Power control apparatus and method for controlling a supply voltage for an associated circuit

#29 | 2011-05-26
US20110121876A1
Electricity

State retention circuit and method of operation of such a circuit

#30 | 2010-04-01
US20100083062A1
Physics

High performance pulsed storage circuit

InventorID:

137092 ⎘