Cary, North Carolina
United States
27
2025-05-22
The entities that hold a legal rights for patent applications filed by inventor Chen Minhan:
Minhan Chen from Cary, US has applied for patents for these inventions. The list has both pending applications and granted patents:
PHASE INTERPOLATOR (PI) INCLUDING WEIGHTED SUMMING CIRCUIT AND RELATED METHODS
#2 | 2025-05-08PHASE INTERPOLATOR (PI) WITH CLAMPING CIRCUIT TO LIMIT OPERATION TO RANGE HAVING OPTIMAL INTEGRAL NON-LINEARITY AND RELATED METHODS
#3 | 2025-05-08TIME TO DIGITAL CONVERTER (TDC) CIRCUIT WITH SELF-ADAPTIVE TIME GRANULARITY AND RELATED METHODS
#4 | 2025-05-01DIGITAL PHASE-LOCKED LOOPS (PLL) INCLUDING CLOSED-LOOP TIME-TO-DIGITAL CONVERTER (TDC) GAIN CALIBRATION CIRCUITS AND RELATED METHODS
#5 | 2024-10-31TIME-TO-DIGITAL CONVERTERS (TDC) EMPLOYING A SINGLE-STAGE DELAY PAIR AND NOISE SHAPING FOR WIDE INPUT RANGE AND REDUCED QUANTIZATION NOISE IN A PHASE-LOCKED LOOP (PLL)
#6 | 2024-08-29Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods
#7 | 2024-08-08PHASE-LOCKED LOOPS (PLL) INCLUDING DIGITALLY CONTROLLED OSCILLATOR (DCO) GAIN CALIBRATION CIRCUITS AND RELATED METHODS
#8 | 2024-02-29Peak voltage amplitude detectors tolerant to process variation and device mismatch and related methods
#9 | 2023-11-30Time to digital converter (TDC) circuit with self-adaptive time granularity and related methods
#10 | 2021-10-26Calibrating a phase interpolator by amplifying timing differences
#11 | 2020-04-02Low-power, low-latency time-to-digital-converter-based serial link
#12 | 2019-12-10Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin
#13 | 2019-06-06Offset nulling for high-speed sense amplifier
#14 | 2018-09-18Apparatus and method for calibrating a receiver with a decision feedback equalizer (DFE)
#15 | 2017-02-09Accurate sample latch offset compensation scheme
#16 | 2016-10-06Offset calibration for low power and high performance receiver
#17 | 2016-07-28BUILT-IN TEST STRUCTURE FOR A RECEIVER
#18 | 2015-12-10Offset calibration for low power and high performance receiver
#19 | 2015-05-14Testing a decision feedback equalizer (‘DFE’)
#20 | 2015-01-15Dynamically calibrating the offset of a receiver with a decision feedback equalizer (DFE) while performing data transport operations
#21 | 2014-12-25Testing a decision feedback equalizer (‘DFE’)
#22 | 2014-12-04Decision feedback equalizer (‘DFE’) with a plurality of independently-controlled isolated power domains
#23 | 2013-03-14Serial link receiver for handling high speed transmissions
#24 | 2012-01-05Variable gain amplifier with reduced power consumption
#25 | 2009-06-11Systems and Arrangements to Provide Input Offset Voltage Compensation
#26 | 2007-11-22Signal detector with calibration circuit arrangement
#27 | 2007-02-15Differential amplifier offset voltage minimization independently from common mode voltage adjustment
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