William E. Speight

Fast and accurate proton therapy dose calculations

Read and write aware cache with a read portion and a write portion of a tag and status array

Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks

Assigning memory to on-chip coherence domains

Techniques for dynamically sharing a fabric to facilitate off-chip communication for multiple on-chip units

Instruction set architecture extensions for performing power versus performance tradeoffs

Assigning memory to on-chip coherence domains

Reducing energy consumption of set associative caches by reducing checked ways of the set association

Latency-tolerant 3D on-chip memory organization

Mechanisms for reducing DRAM power consumption

Stackable module for energy-efficient computing systems

Scalable space-optimized and energy-efficient computing system

Data Reorganization through Hardware-Supported Intermediate Addresses

Cache directed sequential prefetch

Read and write aware cache storing cache lines in a read-often portion and a write-often portion

Fine grained cache allocation

Method and system for performance isolation in virtualized environments

Varying a data prefetch size based upon data usage

Remote asynchronous data mover

Non-uniform cache architecture (NUCA)

Cache directed sequential prefetch

Sourcing differing amounts of prefetch data in response to data prefetch requests

System and Method for Data Processing Using a Low-Cost Two-Tier Full-Graph Interconnect Architecture

Techniques for indirect data prefetching

Data prefetching using indirect addressing

DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT SUPPORT A TOUCH OF A PARTIAL CACHE LINE OF DATA

Jump starting prefetch streams across page boundaries

Dynamic adjustment of prefetch stream priority

Techniques for multi-level indirect data prefetching

Techniques for prediction-based indirect data prefetching

Techniques for data prefetching using indirect addressing with offset

Varying an amount of data retrieved from memory based upon an instruction hint

Complier assisted victim cache bypassing

Address translation through an intermediate address space

Techniques for predicated execution in an out-of-order processor

Hardware based dynamic load balancing of message passing interface tasks by modifying tasks

Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks

System and Method for Hardware Based Dynamic Load Balancing of Message Passing Interface Tasks

Hardware based dynamic load balancing of message passing interface tasks

Method for data processing using a multi-tiered full-graph interconnect architecture

Modifying an operation of one or more processors executing message passing interface tasks

Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture

Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture

Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture

System for data processing using a multi-tiered full-graph interconnect architecture

Branch target address cache

Data processing system, processor and method of data processing having improved branch target address cache

Efficient multiple-table reference prediction mechanism

Dynamically adjusting a pre-fetch distance to enable just-in-time prefetching within a processing system

Complier assisted victim cache bypassing

System and method for contention-based cache performance optimization

System and method of managing cache hierarchies with adaptive mechanisms