Abbas Ali

PHOTORESIST POISONING REDUCTION

CONTROL OF LOCOS STRUCTURE THICKNESS WITHOUT A MASK

METHOD OF REDUCING INTEGRATED DEEP TRENCH OPTICALLY SENSITIVE DEFECTIVITY

FINFET WTRANSISTOR WITH MULTIPLE IMPLANT SPECIES

INTEGRATED DEEP TRENCH HIGH-K CAPACITOR AND METHOD

DEEP TRENCH ISOLATION WITH FIELD OXIDE

Reducing Defects In a Polysilicon Overlaid Fin Structure

CONTROL OF LOCOS STRUCTURE THICKNESS WITHOUT A MASK

MULTI-LOOP TIME VARYING BOSCH PROCESS FOR 2-DIMENSIONAL SMALL CD HIGH ASPECT RATIO DEEP SILICON TRENCH ETCHING

REDUCED SEMICONDUCTOR WAFER BOW AND WARPAGE

Control of locos structure thickness without a mask

MERGED TRENCHES SURROUNDED BY WIDER TRENCH FOR ISOLATING SEMICONDUCTOR DEVICES

THIN FILM RESISTOR MISMATCH IMPROVEMENT USING A SELF-ALIGNED DOUBLE PATTERN (SADP) TECHNIQUE

LOCOS OR SIBLK TO PROTECT DEEP TRENCH POLYSILICON IN DEEP TRENCH AFTER STI PROCESS

DIE SIZE REDUCTION AND DEEP TRENCH DENSITY INCREASE USING DEEP TRENCH ISOLATION AFTER SHALLOW TRENCH ISOLATION INTEGRATION

REDUCED SILICON DISLOCATION DEFECTS FROM DEEP SI TRENCH INTEGRATION

Method of annealing out silicon defectivity

Reduced semiconductor wafer bow and warpage

INTEGRATED CIRCUIT DEVICE WITH IMPROVED OXIDE EDGING

METHOD OF REDUCING INTEGRATED DEEP TRENCH OPTICALLY SENSITIVE DEFECTIVITY

Deep trench isolation with field oxide

Implant blocking for a trench or FinFET without an additional mask

Thin film resistor with punch-through vias

IC with matched thin film resistors

Semiconductor device with deep trench isolation and trench capacitor

Integrated circuits including composite dielectric layer

Semiconductor device with deep trench isolation and trench capacitor

IC with top side capacitor having lateral regions with thinned capacitor dielectric

IC with larger and smaller width contacts

IC with larger and smaller width contacts

Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings

Thin film resistor with punch-through vias

Thin film resistor with punch-through vias

In-situ plasma treatment for thin film resistors

Semiconductor product and fabrication process

Metal interconnect processing for an integrated circuit metal stack

Semiconductor product and fabrication process

Device and method for a thin film resistor using a via retardation layer

SINGLE MASK LEVEL FORMING BOTH TOP-SIDE-CONTACT AND ISOLATION TRENCHES

Anneal after trench sidewall implant to reduce defects

Anneal after trench sidewall implant to reduce defects

Metal interconnect processing for a non-reactive metal stack

Integrated trench capacitor with top plate having reduced voids

Metal thin film resistor and process

Substrate contact having substantially straight sidewalls to a top surface of the substrate

Substrate contact etch process

Deep trench with self-aligned sinker

Very high aspect ratio contact

Metal thin film resistor and process

Method of etching ferroelectric capacitor stack

ETCHING HIGH K DIELECTRIC FILMS WITH REDUCED LIKELIHOOD OF DELAMINATION

Post chromium alloy plasma etch ashing process

Plasma etch for chromium alloys

Method of planarizing a semiconductor device

Process for forming a dual damascene structure

HSQ/SOG dry strip process

BARC/resist via etchback process

Low-K dielectric etch process for dual-damascene structures