Inventor profile of:

Alessia Marelli

City:

Dalmine

Country:

Italy

Published Applications:

25

Last publication date:

2019-06-25

Top Assignees for applications by Alessia Marelli

The entities that hold a legal rights for patent applications filed by inventor Marelli Alessia:

Recent patent applications by Marelli Alessia

Alessia Marelli from Dalmine, IT has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-06-25
US14715403
Physics

Nonvolatile memory system with retention monitor

#2 | 2018-10-18
US20180300088A1
Physics

System and method for randomizing data

#3 | 2018-02-01
US20180034485A1
Electricity

Auto-learning log likelihood ratio

#4 | 2018-02-01
US20180033491A1
Physics

Background reference positioning and local reference positioning using threshold voltage shift read

#5 | 2018-02-01
US20180033490A1
Physics

Nonvolatile memory system with background reference positioning and local reference positioning

#6 | 2017-10-24
US14812891
Physics

Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction

#7 | 2016-09-20
US14557214
Electricity

High quality log likelihood ratios determined using two-index look-up table

#8 | 2016-07-19
US13792831
Electricity

System and method for lifetime specific LDPC decoding

#9 | 2016-01-07
US20160004458A1
Physics

System and method for memory block pool wear leveling

#10 | 2015-09-08
US13752757
Physics

Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values

#11 | 2015-07-28
US13752885
Physics

Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system

#12 | 2015-05-21
US20150143206A1
Electricity

Method for performing error corrections of digital information codified as a symbol sequence

#13 | 2015-03-24
US13785848
Electricity

Layer specific attenuation factor LDPC decoder

#14 | 2014-09-18
US20140281828A1
Electricity

System and method for accumulating soft information in LDPC decoding

#15 | 2014-09-18
US20140281823A1
Physics

System and method with reference voltage partitioning for low density parity check decoding

#16 | 2014-09-18
US20140281800A1
Electricity

System and method for higher quality log likelihood ratios in LDPC decoding

#17 | 2014-04-22
US13023336
-

Nonvolatile memory controller with two-stage error correction technique for enhanced reliability

#18 | 2014-02-18
US13434770
-

Nonvolatile memory controller with concatenated error correction codes

#19 | 2013-12-31
US13435572
-

Nonvolatile memory controller with error detection for concatenated error correction codes

#20 | 2013-03-12
US12913716
-

BCH data correction system and method

#21 | 2011-07-07
US20110167318A1
Physics

Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code

#22 | 2008-05-01
US20080104477A1
Electricity

Method for performing error corrections of digital information codified as a symbol sequence

#23 | 2008-03-13
US20080065937A1
Physics

NAND FLASH MEMORY DEVICE WITH ECC PROTECTED RESERVED AREA FOR NON-VOLATILE STORAGE OF REDUNDANCY DATA

#24 | 2007-10-04
US20070234164A1
Physics

Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code

#25 | 2005-03-03
US20050050434A1
Electricity

Method for performing error corrections of digital information codified as a symbol sequence

InventorID:

1410957 ⎘