Thomas ELMER

SYSTOLIC ARRAY WITH INPUT REDUCTION TO MULTIPLE REDUCED INPUTS

LOGIC GATE COMPLEXITY

LOGIC GATE COMPLEXITY

SIGNIFICAND SHIFTING IN FLOATING POINT PROCESSING OPERATIONS

FLOATING POINT ACCUMULATION

Increasing performance of computational array accelerators

SYSTOLIC ARRAY INCLUDING FUSED MULTIPLY ACCUMULATE WITH EFFICIENT PRENORMALIZATION AND EXTENDED DYNAMIC RANGE

Systolic multiply delayed accumulate processor architecture

Multiple accumulate busses in a systolic array

TRIPLE ADDER

Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range

SYSTOLIC ARRAY WITH INPUT REDUCTION TO MULTIPLE REDUCED INPUTS

Systolic array with efficient input reduction and extended array performance

Multiple accumulate busses in a systolic array

Multiple accumulate busses in a systolic array

Multiple busses interleaved in a systolic array

Parallelism within a systolic array using multiple accumulate busses

Systolic array component combining multiple integer and floating-point data types

Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range

Reducing dynamic power consumption in arrays

Accelerated quantized multiply-and-add operations

Accelerated quantized multiply-and-add operations

Processing denormal numbers in FMA hardware

Chained split execution of fused compound arithmetic operations

Calculation control indicator cache

Calculation control indicator cache

Subdivision of a fused compound arithmetic operation

Split-path heuristic for performing a fused FMA operation

Standard format intermediate result

Temporally split fused multiply-accumulate operation

Non-atomic split-path fused multiply-accumulate