Chapel Hill, North Carolina
United States
23
2020-12-03
The entities that hold a legal rights for patent applications filed by inventor WRIGHT Gregory Michael:
Gregory Michael WRIGHT from Chapel Hill, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Event counter circuits using partitioned moving average determinations and related methods
#2 | 2020-04-02Providing predictive instruction dispatch throttling to prevent resource overflows in out-of-order processor (OOP)-based devices
#3 | 2020-02-27PROVIDING EFFICIENT HANDLING OF BRANCH DIVERGENCE IN VECTORIZABLE LOOPS BY VECTOR-PROCESSOR-BASED DEVICES
#4 | 2020-01-09Providing reconfigurable fusion of processing elements (PEs) in vector-processor-based devices
#5 | 2019-12-19Enabling parallel memory accesses by providing explicit affine instructions in vector-processor-based devices
#6 | 2019-12-05Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices
#7 | 2019-03-21Deadlock free resource management in block based computing architectures
#8 | 2019-03-14Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
#9 | 2019-02-28CACHING INSTRUCTION BLOCK HEADER DATA IN BLOCK ARCHITECTURE PROCESSOR-BASED SYSTEMS
#10 | 2019-01-10SELECTIVE REFRESH MECHANISM FOR DRAM
#11 | 2018-08-16Speculative transitions among modes with different privilege levels in a block-based microarchitecture
#12 | 2018-03-29REUSING TRAINED PREFETCHERS
#13 | 2018-03-22MEMORY VIOLATION PREDICTION
#14 | 2018-03-22PERFORMING DISTRIBUTED BRANCH PREDICTION USING FUSED PROCESSOR CORES IN PROCESSOR-BASED SYSTEMS
#15 | 2018-03-22Providing memory dependence prediction in block-atomic dataflow architectures
#16 | 2017-06-29Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model
#17 | 2017-03-30Providing coherent merging of committed store queue entries in unordered store queues of block-based computer processors
#18 | 2017-03-23CONFIGURING COARSE-GRAINED RECONFIGURABLE ARRAYS (CGRAs) FOR DATAFLOW INSTRUCTION BLOCK EXECUTION IN BLOCK-BASED DATAFLOW INSTRUCTION SET ARCHITECTURES (ISAs)
#19 | 2017-03-02CACHE WAY PREDICTION USING PARTIAL TAGS
#20 | 2016-09-08Register renaming in block-based instruction set architecture
#21 | 2016-08-11FAN OUT OF RESULT OF EXPLICIT DATA GRAPH EXECUTION INSTRUCTION
#22 | 2016-06-23MANAGING ALLOCATION OF PHYSICAL REGISTERS IN A BLOCK-BASED INSTRUCTION SET ARCHITECTURE (ISA), AND RELATED APPARATUSES AND METHODS
#23 | 2016-01-21Fast, Combined Forwards-Backwards Pass Global Optimization Framework for Dynamic Compilers
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