Inventor profile of:

MICHAEL A. SADD

City:

AUSTIN, Texas

Country:

United States

Published Applications:

45

Last publication date:

2026-04-30

Top Assignees for applications by MICHAEL A. SADD

The entities that hold a legal rights for patent applications filed by inventor SADD MICHAEL A.:

Recent patent applications by SADD MICHAEL A.

MICHAEL A. SADD from AUSTIN, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-30
US20260120739A1
Physics

CONFIGURATION BIT HAVING A PLURALITY OF MAGNETORESISTIVE DEVICES, AND METHODS OF PROGRAMMING AND READING THE SAME

#2 | 2025-11-20
US20250356899A1
Physics

ARRAY ARCHITECTURE FOR DISTRIBUTED MRAM

#3 | 2025-10-23
US20250329366A1
Physics

SENSING STANDALONE MTJ WITHOUT BIAS

#4 | 2025-09-18
US20250295040A1
Electricity

MTJ ANTIFUSE WITH TRIM ENABLE AND METHOD OF OPERATION

#5 | 2025-09-18
US20250292850A1
Physics

MAGNETIC TUNNEL JUNCTION ANTI-FUSE INCLUDING NON-MAGNETIC STACK

#6 | 2025-09-18
US20250292849A1
Physics

REFERENCE RESISTOR HAVING VARIABLE RESISTANCE

#7 | 2025-09-18
US20250292815A1
Physics

ANTI-FUSE AND FUSE IN MAGNETORESISTIVE DEVICE

#8 | 2024-12-19
US20240420796A1
Physics

DISTRIBUTED MRAM CONFIGURATION BIT AND METHOD OF REPAIR

#9 | 2023-11-16
US20230368859A1
Physics

Testing disruptive memories

#10 | 2022-07-28
US20220238153A1
Physics

Memory with sense amplifiers

#11 | 2019-03-05
US15894399
Physics

Memory with a global reference circuit

#12 | 2018-01-18
US20180019735A1
Electricity

Systems and methods for non-volatile flip flops

#13 | 2017-12-19
US15356877
Physics

Resistive non-volatile memory and a method for sensing a memory cell in a resistive non-volatile memory

#14 | 2017-11-30
US20170345491A1
Physics

Systems and methods for non-volatile flip flops

#15 | 2017-11-23
US20170337960A1
Physics

Sense path circuitry suitable for magnetic tunnel junction memories

#16 | 2017-10-03
US15356879
Physics

Magnetic random access memory (MRAM) and method of operation

#17 | 2017-08-22
US15293335
Physics

Sense amplifier circuit

#18 | 2017-08-22
US15281400
Physics

Sense amplifier circuit

#19 | 2017-05-02
US15165041
Physics

Nonvolatile static random access memory (NVSRAM) system having a static random access memory (SRAM) array and a resistive memory array

#20 | 2017-04-27
US20170117028A1
Physics

Sense path circuitry suitable for magnetic tunnel junction memories

#21 | 2017-03-14
US14885688
Physics

Non-volatile random access memory (NVRAM) with backup control

#22 | 2017-03-02
US20170063348A1
Electricity

Programmable resistive elements as variable tuning elements

#23 | 2017-03-02
US20170062052A1
Physics

Ternary content addressable memory (TCAM) with programmable resistive elements

#24 | 2017-03-02
US20170062049A1
Physics

Static random access memory (SRAM) with programmable resistive elements

#25 | 2017-02-16
US20170047098A1
Physics

Non-volatile dynamic random access memory (NVDRAM) with programming line

#26 | 2016-12-13
US15057004
Physics

Magnetic random access memory (MRAM) and method of operation

#27 | 2016-12-06
US15018095
Physics

Resistive non-volatile memory cell and method for programming same

#28 | 2016-12-06
US14807157
Electricity

Programmable resistive elements as variable tuning elements

#29 | 2016-11-24
US20160343436A1
Physics

Systems and methods for SRAM with backup non-volatile memory that includes MTJ resistive elements

#30 | 2016-08-25
US20160246539A1
Physics

Memory device with combined non-volatile memory (NVM) and volatile memory

#31 | 2016-05-26
US20160148685A1
Physics

Resistive memory with program verify and erase verify capability

#32 | 2016-01-21
US20160019964A1
Physics

Memory device with combined non-volatile memory (NVM) and volatile memory

#33 | 2012-09-27
US20120241909A1
Electricity

Low-leakage, high-capacitance capacitor structures and method of making

#34 | 2012-05-10
US20120113714A1
Physics

Method for programming a multi-state non-volatile memory (NVM)

#35 | 2012-01-19
US20120014179A1
Physics

Soft program of a non-volatile memory block

#36 | 2009-02-12
US20090042349A1
Performing operations; transporting

Split gate memory cell and method therefor

#37 | 2007-08-02
US20070178649A1
Electricity

Double-gated non-volatile memory and methods for forming thereof

#38 | 2007-06-14
US20070134888A1
Electricity

Back-gated semiconductor device with a storage layer and methods for forming thereof

#39 | 2007-06-14
US20070134867A1
Electricity

Floating gate non-volatile memory and method thereof

#40 | 2007-04-19
US20070085153A1
Electricity

Voltage controlled oscillator with a multiple gate transistor and method therefor

#41 | 2007-04-05
US20070077705A1
Performing operations; transporting

Split gate memory cell and method therefor

#42 | 2007-01-25
US20070020856A1
Electricity

Process for forming an electronic device including discontinuous storage elements

#43 | 2007-01-25
US20070018222A1
Electricity

Electronic device including discontinuous storage elements

#44 | 2006-02-09
US20060030105A1
Performing operations; transporting

Method of discharging a semiconductor device

#45 | 2005-01-25
US10601256
-

Memory with multiple state cells and sensing method

InventorID:

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