Robert J. Allen

Model order reduction in transistor level timing

COGNITIVE SYSTEM TO ITERATIVELY EXPAND A KNOWLEDGE BASE

Model order reduction in transistor level timing

Multi-sided variations for creating integrated circuits

Multi-sided variations for creating integrated circuits

Multi-sided variations for creating integrated circuits

Process for improving capacitance extraction performance

Multi-cycle signal identification for static timing analysis

Process for improving capacitance extraction performance

Multi-cycle signal identification for static timing analysis

Timing analysis of circuits using sub-circuit timing models

Model order reduction in transistor level timing

Generating asserted sensitivities for statistical timing

Technology migration for integrated circuits with radical design restrictions

IC layout optimization to improve yield

Critical area computation of composite fault mechanisms using Voronoi diagrams

Content based yield prediction of VLSI designs

Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design

Method for computing the critical area of compound fault mechanisms

Method and apparatus for manufacturing diamond shaped chips

IC layout optimization to improve yield

Technology migration for integrated circuits with radical design restrictions

Critical area computation of composite fault mechanisms using Voronoi diagrams

Method and apparatus for manufacturing diamond shaped chips

Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs

Technology migration for integrated circuits with radical design restrictions

Content based yield prediction of VLSI designs

Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing

Sample probability of fault function determination using critical defect size map

Probability of fault function determination using critical defect size map

Integrated circuit yield enhancement using Voronoi diagrams

Technology migration for integrated circuits with radical design restrictions

Technology migration for integrated circuits with radical design restrictions

Integrated circuit macro placing system and method

Generation of refined switching windows in static timing analysis

Practical method for hierarchical-preserving layout optimization of integrated circuit layout

IC tiling pattern method, IC so formed and analysis method

Critical area computation of composite fault mechanisms using voronoi diagrams

Simplified tiling pattern method

Method for improving chip yields in the presence of via flaring

THE USE OF A LAYOUT-OPTIMIZATION TOOL TO INCREASE THE YIELD AND RELIABILITY OF VLSI DESIGNS

Use of a layout-optimization tool to increase the yield and reliability of VLSI designs

THE USE OF A LAYOUT-OPTIMIZATION TOOL TO INCREASE THE YIELD AND RELIABILITY OF VLSI DESIGNS