Newark, California
United States
24
2019-01-24
The entities that hold a legal rights for patent applications filed by inventor Krishnan Siddarth A.:
Siddarth A. Krishnan from Newark, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Shared metal gate stack with tunable work function
#2 | 2018-11-15FIELD EFFECT TRANSISTOR GATE STACK
#3 | 2018-07-05Shared metal gate stack with tunable work function
#4 | 2018-04-12Integrated circuit with replacement gate stacks and method of forming same
#5 | 2018-04-05Integrated circuit with replacement gate stacks and method of forming same
#6 | 2017-12-14Shared metal gate stack with tunable work function
#7 | 2017-08-17INTEGRATED CIRCUIT HAVING IMPROVED ELECTROMIGRATION PERFORMANCE AND METHOD OF FORMING SAME
#8 | 2017-07-20Semiconductor device having a gate stack with tunable work function
#9 | 2017-07-20Field effect transistor gate stack
#10 | 2017-07-20Field effect transistor stack with tunable work function
#11 | 2017-06-22Method to form dual tin layers as pFET work metal stack
#12 | 2017-06-13Integrated circuit having improved electromigration performance and method of forming same
#13 | 2017-05-25Forming a semiconductor structure for reduced negative bias temperature instability
#14 | 2017-05-11Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
#15 | 2017-04-20Integrated circuit with replacement gate stacks and method of forming same
#16 | 2017-02-28Gate stack with tunable work function
#17 | 2017-02-21Forming a semiconductor structure for reduced negative bias temperature instability
#18 | 2017-02-16Field effect transistors having multiple effective work functions
#19 | 2017-01-31Semiconductor device having a gate stack with tunable work function
#20 | 2016-12-01Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme
#21 | 2016-11-22Forming a semiconductor structure for reduced negative bias temperature instability
#22 | 2016-07-19Methods of forming multi-Vt III-V TFET devices
#23 | 2016-06-30Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme
#24 | 2016-02-18Method of patterning dopant films in high-K dielectrics in a soft mask integration scheme
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