Fishkill, New York
United States
17
2026-02-05
The entities that hold a legal rights for patent applications filed by inventor RAO Vasant:
Vasant RAO from Fishkill, US has applied for patents for these inventions. The list has both pending applications and granted patents:
AUTOMATED SIGNAL ELECTROMIGRATION VIOLATION RESOLUTION FOR LOGIC CIRCUIT DESIGNS
#2 | 2025-08-14AUTOMATED SIGNAL ELECTROMIGRATION ANALYSIS FOR LOGIC CIRCUIT DESIGN
#3 | 2024-10-03LOCATION AWARE TIMING ANALYSIS OF A DIGITAL INTEGRATED CIRCUIT
#4 | 2019-10-31Model order reduction in transistor level timing
#5 | 2018-12-27Model order reduction in transistor level timing
#6 | 2017-06-15Deterministic and statistical timing modeling for differential circuits
#7 | 2017-02-16Prioritized path tracing in statistical timing analysis of integrated circuits
#8 | 2016-03-24Model order reduction in transistor level timing
#9 | 2012-07-19Method for improving static timing analysis and optimizing circuits using reverse merge
#10 | 2011-09-15Modeling loading effects of a transistor network
#11 | 2011-07-07Timing point selection for a static timing analysis in the presence of interconnect electrical elements
#12 | 2009-07-16System and method for improved hierarchical analysis of electronic circuits
#13 | 2008-06-12Affinity-based clustering of vectors for partitioning the columns of a matrix
#14 | 2007-11-29Affinity-based clustering of vectors for partitioning the columns of a matrix
#15 | 2007-10-04Multiple mode approach to building static timing models for digital transistor circuits
#16 | 2006-09-14Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect
#17 | 2005-04-28Affinity-based clustering of vectors for partitioning the columns of a matrix
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