Poughkeepsie, New York
United States
9
2016-03-24
The entities that hold a legal rights for patent applications filed by inventor SOREFF Jeffrey P.:
Jeffrey P. SOREFF from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Model order reduction in transistor level timing
#2 | 2012-10-18Delay model construction in the presence of multiple input switching events
#3 | 2011-09-15Modeling loading effects of a transistor network
#4 | 2011-07-07Timing point selection for a static timing analysis in the presence of interconnect electrical elements
#5 | 2009-07-16System and method for improved hierarchical analysis of electronic circuits
#6 | 2007-10-04Multiple mode approach to building static timing models for digital transistor circuits
#7 | 2006-09-14Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect
#8 | 2005-03-31Methods for modeling latch transparency
#9 | 2005-03-31Methods for modeling latch transparency
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