David Albert Carlson

Managing potential faults for speculative page table access

Managing commit order for an external instruction relative to queued instructions

Managing load and store instructions for memory barrier handling

Managing trace information storage using pipeline instruction insertion and filtering

Managing commit order for an external instruction relative to two unissued queued instructions

Managing low-level instructions and core interactions in multi-core processors

Managing memory access requests with prefetch for streams

Managing fairness for lock and unlock operations using operation prioritization

Managing lock and unlock operations using active spinning

Managing lock and unlock operations using traffic prioritization

Managing lock and unlock operations using operation prediction

Managing virtual-address caches for multiple memory page sizes

Admission control for memory access requests

Managing memory access requests with prefetch for streams

Managing history information for branch prediction

Flexible instruction execution in a processor pipeline

Flexible instruction execution in a processor pipeline

MANAGING INSTRUCTION ORDER IN A PROCESSOR PIPELINE

MANAGING INSTRUCTION ORDER IN A PROCESSOR PIPELINE