Inventor profile of:

Markus Helms

City:

BOEBLINGEN

Country:

Germany

Published Applications:

28

Last publication date:

2023-12-14

Top Assignees for applications by Markus Helms

The entities that hold a legal rights for patent applications filed by inventor Helms Markus:

Recent patent applications by Helms Markus

Markus Helms from BOEBLINGEN, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-12-14
US20230401161A1
Physics

Translation support for a virtual cache

#2 | 2020-05-21
US20200159670A1
Physics

Multi-engine address translation facility

#3 | 2020-03-19
US20200089754A1
Physics

Memory preserving parse tree based compression with entropy coding

#4 | 2019-09-19
US20190286573A1
Physics

Suspending translation look-aside buffer purge execution in a multi-processor environment

#5 | 2019-08-22
US20190258588A1
Physics

Zone-SDID mapping scheme for TLB purges

#6 | 2019-08-08
US20190243894A1
Physics

Memory preserving parse tree based compression with entropy coding

#7 | 2019-08-01
US20190236025A1
Physics

Multi-engine address translation facility

#8 | 2019-08-01
US20190236024A1
Physics

Multi-engine address translation facility

#9 | 2018-12-20
US20180365172A1
Physics

Translation support for a virtual cache

#10 | 2018-12-20
US20180365171A1
Physics

Incorporating purge history into least-recently-used states of a translation lookaside buffer

#11 | 2018-12-20
US20180365170A1
Physics

Translation support for a virtual cache

#12 | 2018-12-20
US20180365169A1
Physics

Incorporating purge history into least-recently-used states of a translation lookaside buffer

#13 | 2018-12-20
US20180365166A1
Physics

Suspending translation look-aside buffer purge execution in a multi-processor environment

#14 | 2018-12-20
US20180365165A1
Physics

Suspending translation look-aside buffer purge execution in a multi-processor environment

#15 | 2018-12-20
US20180365164A1
Physics

Sharing virtual and real translations in a virtual cache

#16 | 2018-12-20
US20180365162A1
Physics

Suspending translation look-aside buffer purge execution in a multi-processor environment

#17 | 2018-12-20
US20180365161A1
Physics

Sharing virtual and real translations in a virtual cache

#18 | 2018-12-13
US20180357182A1
Physics

Zone-SDID mapping scheme for TLB purges

#19 | 2018-12-13
US20180357181A1
Physics

Zone-SDID mapping scheme for TLB purges

#20 | 2018-09-27
US20180276138A1
Physics

Translating virtual memory addresses to physical addresses

#21 | 2018-09-13
US20180260337A1
Physics

Multi-engine address translation facility

#22 | 2018-09-13
US20180260336A1
Physics

Multi-engine address translation facility

#23 | 2017-06-08
US20170163283A1
Electricity

Memory preserving parse tree based compression with entropy coding

#24 | 2017-06-08
US20170161362A1
Physics

Memory preserving parse tree based compression with entropy coding

#25 | 2016-04-28
US20160117200A1
Physics

Resource mapping in multi-threaded central processor units

#26 | 2016-04-28
US20160117193A1
Physics

Resource mapping in multi-threaded central processor units

#27 | 2006-02-09
US20060029088A1
Electricity

Reducing latency in a channel adapter by accelerated I/O control block processing

#28 | 2006-01-19
US20060013397A1
Electricity

Channel adapter managed trusted queue pairs

InventorID:

1513175 ⎘