Schoenaich
Germany
41
2025-12-04
The entities that hold a legal rights for patent applications filed by inventor Klein Michael:
Michael Klein from Schoenaich, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
CONVERT INSTRUCTION WITH OVERFLOW RESULT CONTROL
#2 | 2025-10-23INSTRUCTION WITH A PRESERVE SIGN CONTROL
#3 | 2025-10-02VECTOR TEST ZONED INSTRUCTION FOR VALIDITY TESTING
#4 | 2025-10-02VECTOR TEST DECIMAL INSTRUCTION FOR VALIDITY TESTING
#5 | 2025-09-30Vector test decimal instruction for validity testing
#6 | 2023-10-05Verifying the correctness of a leading zero counter
#7 | 2023-10-05Rounding hexadecimal floating point numbers using binary incrementors
#8 | 2023-09-28REDUCED LOGIC CONVERSION OF BINARY INTEGERS TO BINARY CODED DECIMALS
#9 | 2023-09-21FLOATING-POINT CONVERSION WITH DENORMALIZATION
#10 | 2023-09-14HARDWARE DEVICE TO EXECUTE INSTRUCTION TO CONVERT INPUT VALUE FROM ONE DATA FORMAT TO ANOTHER DATA FORMAT
#11 | 2023-09-14HARDWARE DEVICE TO EXECUTE INSTRUCTION TO CONVERT INPUT VALUE FROM ONE DATA FORMAT TO ANOTHER DATA FORMAT
#12 | 2023-08-31DYNAMIC ALGORITHM SELECTION
#13 | 2022-09-08Hexadecimal floating point multiply and add instruction
#14 | 2022-09-01Vector pack and unpack instructions
#15 | 2022-01-06Repurposed hexadecimal floating point data path
#16 | 2021-03-11Reusing adjacent SIMD unit for fast wide result generation
#17 | 2021-02-18PARTIAL PRODUCT FLOATING-POINT MULTIPLICATION CIRCUITRY OPERAND SUMMATION
#18 | 2021-02-11Efficient checking of a condition code anticipator for a floating point processor and/or unit
#19 | 2021-02-04Repurposed hexadecimal floating point data path
#20 | 2020-11-05Hexadecimal exponent alignment for binary floating point unit
#21 | 2020-11-05Fault-tolerant clock gating
#22 | 2020-10-29Integrated circuit control latch protection
#23 | 2020-06-25Method and apparatus for wiring multiple technology evaluation circuits
#24 | 2019-07-11Parallel decimal multiplication hardware with a 3x generator
#25 | 2019-05-30Parallel decimal multiplication hardware with a 3X generator
#26 | 2019-01-17Multiply-add operations of binary numbers in an arithmetic unit
#27 | 2019-01-17Multiply-add operations of binary numbers in an arithmetic unit
#28 | 2019-01-17Multiply-add operations of binary numbers in an arithmetic unit
#29 | 2019-01-01Rapid character substring searching
#30 | 2018-07-26Combining of several execution units to compute a single wide scalar result
#31 | 2018-03-29Computing and summing up multiple products in a single multiplier
#32 | 2017-08-03Binary fused multiply-add floating-point calculations
#33 | 2017-08-03Binary fused multiply-add floating-point calculations
#34 | 2016-12-08USING ERROR CORRECTING CODES FOR PARITY PURPOSES
#35 | 2016-06-16Non-local error detection in processor systems
#36 | 2016-06-16Non-local error detection in processor systems
#37 | 2016-05-12Using error correcting codes for parity purposes
#38 | 2016-05-12Using error correcting codes for parity purposes
#39 | 2010-07-08Reuse of rounder for fixed conversion of log instructions
#40 | 2010-06-10Residue calculation with built-in correction in a floating point unit positioned at different levels using correction values provided by multiplexer
#41 | 2010-03-11Normalizer shift prediction for log estimate instructions
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