Inventor profile of:

Andrei WARKENTIN

City:

Wakefield, Massachusetts

Country:

United States

Published Applications:

16

Last publication date:

2018-12-13

Top Assignees for applications by Andrei WARKENTIN

The entities that hold a legal rights for patent applications filed by inventor WARKENTIN Andrei:

Recent patent applications by WARKENTIN Andrei

Andrei WARKENTIN from Wakefield, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-12-13
US20180357070A1
Physics

Intelligent UEFI run-time services address space management

#2 | 2018-06-21
US20180173646A1
Physics

Memory management in virtualized computing systems having processors with more than two hierarchical privilege levels

#3 | 2017-12-21
US20170364379A1
Physics

Hypervisor backdoor interface

#4 | 2017-12-21
US20170364365A1
Physics

Multiprocessor initialization via firmware configuration

#5 | 2017-03-02
US20170060765A1
Physics

Implementing per-processor memory areas with non-preemptible operations using virtual aliases

#6 | 2017-03-02
US20170060613A1
Physics

Partitioning a hypervisor into virtual hypervisors

#7 | 2016-12-29
US20160378696A1
Physics

Exposing memory-mapped IO devices to drivers by emulating PCI bus and PCI device configuration space

#8 | 2016-10-11
US14753720
Physics

Implementing upcall from secure to non-secure mode by injecting exception into non-secure mode

#9 | 2016-10-06
US20160291986A1
Physics

Exposing memory-mapped IO devices to drivers through firmware

#10 | 2016-06-16
US20160170912A1
Physics

Safely discovering secure monitors and hypervisor implementations in systems operable at multiple hierarchical privilege levels

#11 | 2016-06-16
US20160170816A1
Physics

Creating a communication channel between different privilege levels using wait-for-event instruction in systems operable at multiple levels hierarchical privilege levels

#12 | 2016-06-16
US20160170679A1
Physics

Secondary CPU MMU initialization using page fault exception

#13 | 2015-12-24
US20150371036A1
Physics

Device simulation in a secure mode supported by hardware architectures

#14 | 2015-12-24
US20150370592A1
Physics

Hypervisor context switching using TLB tags in processors having more than two hierarchical privilege levels

#15 | 2015-12-24
US20150370591A1
Physics

Hypervisor context switching using a redirection exception vector in processors having more than two hierarchical privilege levels

#16 | 2015-12-24
US20150370590A1
Physics

Hypervisor context switching using a trampoline scheme in processors having more than two hierarchical privilege levels

InventorID:

1563559 ⎘