Mountain View, California
United States
86
2023-03-02
The entities that hold a legal rights for patent applications filed by inventor Arthur John V.:
John V. Arthur from Mountain View, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Runtime reconfigurable neural network processor core
#2 | 2021-10-07Neural network weight distribution from a grid of memory elements
#3 | 2021-07-08COMPRESSED WEIGHT DISTRIBUTION IN NETWORKS OF NEURAL PROCESSORS
#4 | 2021-06-10Flexible precision neural inference processing unit
#5 | 2021-06-03Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network
#6 | 2021-04-293D NEURAL INFERENCE PROCESSING UNIT ARCHITECTURES
#7 | 2021-04-15Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine
#8 | 2020-12-03Performing error detection during deterministic program execution
#9 | 2020-11-19Globally asynchronous and locally synchronous (GALS) neuromorphic network
#10 | 2020-06-25Massively parallel neural inference computing elements
#11 | 2020-05-28Compound instruction set architecture for a neural inference chip
#12 | 2020-04-16Networks for distributing parameters and data to neural network compute cores
#13 | 2020-04-16Data representation for dynamic precision in neural network cores
#14 | 2020-04-16MULTI-AGENT INSTRUCTION EXECUTION ENGINE FOR NEURAL INFERENCE PROCESSING
#15 | 2020-04-02Data distribution in an array of neural network cores
#16 | 2020-02-06SCHEDULER FOR MAPPING NEURAL NETWORKS ONTO AN ARRAY OF NEURAL CORES IN AN INFERENCE PROCESSING UNIT
#17 | 2020-01-16HIERARCHICAL PARALLELISM IN A NETWORK OF DISTRIBUTED NEURAL NETWORK CORES
#18 | 2020-01-09Instruction distribution in an array of neural network cores
#19 | 2020-01-02Memory-mapped interface to message-passing computing systems
#20 | 2019-12-19Runtime reconfigurable neural network processor core
#21 | 2019-12-19Parallel computational architecture with reconfigurable core-level and vector-level parallelism
#22 | 2019-10-31CENTRAL SCHEDULER AND INSTRUCTION DISPATCHER FOR A NEURAL INFERENCE PROCESSOR
#23 | 2019-10-24TIME, SPACE, AND ENERGY EFFICIENT NEURAL INFERENCE VIA PARALLELISM AND ON-CHIP MEMORY
#24 | 2019-10-03Massively parallel neural inference computing elements
#25 | 2019-10-03Defect resistant designs for location-sensitive neural network processor arrays
#26 | 2019-10-03BLOCK TRANSFER OF NEURON OUTPUT VALUES THROUGH DATA MEMORY FOR NEUROSYNAPTIC PROCESSORS
#27 | 2019-09-26Peripheral device interconnections for neurosynaptic systems
#28 | 2019-07-25Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network
#29 | 2019-06-27Hardware architecture for simulating a neural network of neurons
#30 | 2019-05-23Scalable neural hardware for the noisy-OR model of Bayesian networks
#31 | 2019-04-25Hardware-software co-design of neurosynaptic systems
#32 | 2019-04-25Memory-mapped interface for message passing computing systems
#33 | 2018-10-04Yield tolerance in a neurosynaptic system
#34 | 2018-08-16Dual deterministic and stochastic neurosynaptic core circuit
#35 | 2018-07-26Providing transposable access to a synapse array using a recursive array layout
#36 | 2018-07-05Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array
#37 | 2018-04-26Mapping neural dynamics of a neural model on to a coarsely grained look-up table
#38 | 2018-04-12Scaling multi-core neurosynaptic networks across chip boundaries
#39 | 2018-03-22Converting spike event data to digital numeric data
#40 | 2018-03-22Converting digital numeric data to spike event data
#41 | 2017-10-05Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency
#42 | 2017-07-13Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs
#43 | 2017-05-04Array of processor core circuits with reversible tiers
#44 | 2017-03-16Neuromorphic network comprising asynchronous routers and synchronous core circuits
#45 | 2017-03-09Dual deterministic and stochastic neurosynaptic core circuit
#46 | 2016-12-08Hardware architecture for simulating a neural network of neurons
#47 | 2016-11-03Yield tolerance in a neurosynaptic system
#48 | 2016-11-03Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network
#49 | 2016-11-03Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits
#50 | 2016-09-08Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation
#51 | 2016-08-18Faulty core recovery mechanisms for a three-dimensional network on a processor array
#52 | 2016-08-11Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array
#53 | 2016-08-04Scaling multi-core neurosynaptic networks across chip boundaries
#54 | 2016-08-04Neuromorphic event-driven neural computing architecture in a scalable neural network
#55 | 2016-06-02Faulty core recovery mechanisms for a three-dimensional network on a processor array
#56 | 2016-05-26Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array
#57 | 2016-04-21Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network
#58 | 2016-03-24Self-timed, event-driven neurosynaptic core controller
#59 | 2016-03-24Converting spike event data to digital numeric data
#60 | 2016-03-24Converting digital numeric data to spike event data
#61 | 2016-02-25Peripheral device interconnections for neurosynaptic systems
#62 | 2016-02-04Hardware architecture for simulating a neural network of neurons
#63 | 2015-12-31Scalable neural hardware for the noisy-OR model of Bayesian networks
#64 | 2015-12-31Providing transposable access to a synapse array using a recursive array layout
#65 | 2015-12-31Multiplexing physical neurons to optimize power and area
#66 | 2015-11-12Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation
#67 | 2015-10-22Globally asynchronous and locally synchronous (GALS) neuromorphic network
#68 | 2015-10-08Scalable neural hardware for the noisy-OR model of Bayesian networks
#69 | 2015-10-08Providing transposable access to a synapse array using a recursive array layout
#70 | 2015-10-01Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs
#71 | 2015-09-17Neuromorphic event-driven neural computing architecture in a scalable neural network
#72 | 2015-09-10Multiplexing physical neurons to optimize power and area
#73 | 2015-08-13Mapping neural dynamics of a neural model on to a coarsely grained look-up table
#74 | 2015-02-05Dual deterministic and stochastic neurosynaptic core circuit
#75 | 2014-11-20Providing transposable access to a synapse array using column aggregation
#76 | 2014-08-28Array of processor core circuits with reversible tiers
#77 | 2014-08-07Consolidating multiple neurosynaptic cores into one memory
#78 | 2014-06-26Hardware architecture for simulating a neural network of neurons
#79 | 2014-06-26Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network
#80 | 2014-06-26Mapping neural dynamics of a neural model on to a coarsely grained look-up table
#81 | 2014-06-26Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation
#82 | 2014-04-24Low-power event-driven neural computing architecture in neural networks
#83 | 2014-04-03Final faulty core recovery mechanisms for a two-dimensional network on a processor array
#84 | 2014-04-03Faulty core recovery mechanisms for a three-dimensional network on a processor array
#85 | 2013-03-21Neuromorphic event-driven neural computing architecture in a scalable neural network
#86 | 2012-06-14Integrate and fire electronic neurons
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