Jonathan Friedmann

Coarse-grain reconfigurable array processor with concurrent handling of multiple graphs on a single grid

Run-Time Parallelization of Code Execution Based on an Approximate Register-Access Specification

MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS

Single-thread processing of multiple code regions

MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS

FLUSHING IN A PARALLELIZED PROCESSOR

SEQUENTIAL MONITORING AND MANAGEMENT OF CODE SEGMENTS FOR RUN-TIME PARALLELIZATION

PROCESSOR WITH EFFICIENT REORDER BUFFER (ROB) MANAGEMENT

SINGLE-THREAD SPECULATIVE MULTI-THREADING

Run-Time Code Parallelization with Monitoring of Repetitive Instruction Sequences During Branch Mis-Prediction

SPECULATIVE MULTI-THREADING TRACE PREDICTION

HARDWARE-BASED RUN-TIME MITIGATION OF BLOCKS HAVING MULTIPLE CONDITIONAL BRANCHES

Hardware-based run-time mitigation of conditional branches

PROCESSOR WITH EFFICIENT PROCESSING OF LOAD-STORE INSTRUCTION PAIRS

PROCESSOR WITH EFFICIENT PROCESSING OF RECURRING LOAD INSTRUCTIONS

Processor with efficient processing of recurring load instructions from nearby memory addresses

Processor with efficient memory access

Run-time parallelization of code execution based on an approximate register-access specification

Parallelized execution of instruction sequences based on pre-monitoring

Parallelized execution of instruction sequences

Early termination of segment monitoring in run-time code parallelization

Run-time code parallelization with continuous monitoring of repetitive instruction sequences

Run-time code parallelization with approximate monitoring of instruction sequences

Run-time code parallelization with monitoring of repetitive instruction sequences during branch mis-prediction