Hemel Hempstead
United Kingdom
30
2025-05-15
The entities that hold a legal rights for patent applications filed by inventor Singleton Iain:
Iain Singleton from Hemel Hempstead, GB has applied for patents for these inventions. The list has both pending applications and granted patents:
Out-of-Bounds Recovery Circuit
#2 | 2025-04-03ASSESSING PERFORMANCE OF A HARDWARE DESIGN USING FORMAL EVALUATION LOGIC
#3 | 2024-12-12DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION
#4 | 2024-10-03LIVELOCK DETECTION IN A HARDWARE DESIGN USING FORMAL EVALUATION LOGIC
#5 | 2024-01-18Detecting out-of-bounds violations in a hardware design using formal verification
#6 | 2023-06-29Out-of-bounds recovery circuit
#7 | 2023-03-30Assessing performance of a hardware design using formal evaluation logic
#8 | 2023-02-02Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known state
#9 | 2022-09-01Livelock detection in a hardware design using formal evaluation logic
#10 | 2022-05-05Formal verification tool to verify hardware design of memory unit
#11 | 2022-05-05Detecting out-of-bounds violations in a hardware design using formal verification
#12 | 2021-09-23Out-of-bounds recovery circuit
#13 | 2021-06-17Assessing performance of a hardware design using formal evaluation logic
#14 | 2021-06-03Detecting out-of-bounds violations in a hardware design using formal verification
#15 | 2021-04-22Livelock detection in a hardware design using formal evaluation logic
#16 | 2021-01-07Out-of-bounds recovery circuit
#17 | 2020-11-05Detecting out-of-bounds violations in a hardware design using formal verification
#18 | 2020-06-11Formal verification tool to verify hardware design of memory unit
#19 | 2020-05-14Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known state
#20 | 2019-09-05Livelock detection in a hardware design using formal evaluation logic
#21 | 2019-09-05Assessing performance of a hardware design using formal evaluation logic
#22 | 2018-04-19Detecting out-of-bounds violations in a hardware design using formal verification
#23 | 2018-04-19Out-of-bounds recovery circuit
#24 | 2017-12-21Livelock detection in a hardware design using formal evaluation logic
#25 | 2017-12-21Livelock recovery circuit configured to detect illegal repetition of an instruction and transition to a known state
#26 | 2017-11-30Assessing performance of a hardware design using formal evaluation logic
#27 | 2017-07-20Dynamic power measurement using formal
#28 | 2017-06-22Arbiter verification
#29 | 2017-05-11Hardware monitor to verify memory units
#30 | 2016-07-21Arbiter verification
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