Underhill, Vermont
United States
45
2015-05-14
The entities that hold a legal rights for patent applications filed by inventor McDevitt Thomas L.:
Thomas L. McDevitt from Underhill, US has applied for patents for these inventions. The list has both pending applications and granted patents:
METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR STRUCTURE
#2 | 2014-04-17System and method for forming an aluminum fuse for compatibility with copper BEOL interconnect scheme
#3 | 2014-02-06TOP CORNER ROUNDING OF DAMASCENE WIRE FOR INSULATOR CRACK SUPPRESSION
#4 | 2014-01-16Integrated circuit switches, design structure and methods of fabricating the same
#5 | 2014-01-16Vertical integrated circuit switches, design structure and methods of fabricating same
#6 | 2013-12-05System and method for forming aluminum fuse for compatibility with copper BEOL interconnect scheme
#7 | 2013-07-04STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION
#8 | 2013-06-20Horizontal coplanar switches and methods of manufacture
#9 | 2013-06-13Locally tailoring chemical mechanical polishing (CMP) polish rate for dielectrics
#10 | 2013-05-30Top corner rounding of damascene wire for insulator crack suppression
#11 | 2013-03-28Structure and method for reducing vertical crack propagation
#12 | 2012-12-20CORNER-ROUNDED STRUCTURES AND METHODS OF MANUFACTURE
#13 | 2012-10-18REINFORCED VIA FARM INTERCONNECT STRUCTURE, A METHOD OF FORMING A REINFORCED VIA FARM INTERCONNECT STRUCTURE AND A METHOD OF REDESIGNING AN INTEGRATED CIRCUIT CHIP TO INCLUDE SUCH A REINFORCED VIA FARM INTERCONNECT STRUCTURE
#14 | 2012-06-14Electrical fuse with a current shunt
#15 | 2012-05-24STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
#16 | 2012-03-15Method of fabricating copper damascene and dual damascene interconnect wiring
#17 | 2012-02-02Horizontal coplanar switches and methods of manufacture
#18 | 2011-06-02WIRING STRUCTURE AND METHOD
#19 | 2011-03-03Integrated circuit switches, design structure and methods of fabricating the same
#20 | 2010-10-21Vertical integrated circuit switches, design structure and methods of fabricating same
#21 | 2010-09-30CMP method
#22 | 2010-03-04Copper damascene and dual damascene interconnect wiring
#23 | 2010-02-11Structures and methods for improving solder bump connections in semiconductor devices
#24 | 2009-11-26Curvilinear wiring structure to reduce areas of high field density in an integrated circuit
#25 | 2009-08-27Methods of manufacturing semiconductor devices and a semiconductor structure
#26 | 2008-06-19LOCAL PLASMA PROCESSING
#27 | 2008-03-13Crack stop for low K dielectrics
#28 | 2007-07-05Metal seed layer deposition
#29 | 2007-06-07Dual damascene wiring and method
#30 | 2007-03-15Method of fabricating copper damascene and dual damascene interconnect wiring
#31 | 2007-02-22Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing
#32 | 2006-11-30Local plasma processing
#33 | 2006-08-08Copper to aluminum interlayer interconnect using stud and via liner
#34 | 2006-07-27Bilayer aluminum last metal for interconnects and wirebond pads
#35 | 2006-05-11Crack stop for low K dielectrics
#36 | 2006-05-02Copper to aluminum interlayer interconnect using stud and via liner
#37 | 2006-03-23Method of fabricating copper damascene and dual damascene interconnect wiring
#38 | 2006-02-09Exposed pore sealing post patterning
#39 | 2006-01-19Dual damascene wiring and method
#40 | 2005-12-01Exposed pore sealing post patterning
#41 | 2005-11-17Metal seed layer deposition
#42 | 2005-09-20Insulative cap for laser fusing
#43 | 2005-09-08Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing
#44 | 2005-05-12Method for fabricating a triple damascene fuse
#45 | 2005-02-03CRACK STOP FOR LOW K DIELECTRICS
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